Electrical and Computer: Electrical and Electronics
The electrical and electronics domain of the FE Electrical and Computer exam tests linear circuit analysis and analog electronic design. Expect node and mesh equations, Thévenin equivalents, phasors and impedance, op-amp circuits, diode and transistor bias, small-signal models, and Bode plots. The central skill is choosing the right model and then checking that the device is still operating where that model applies.
Circuit laws and ac steady state
- Use nodal analysis for circuits with many parallel branches; use mesh analysis for mostly series loops. Dependent sources add one constraint equation each.
- In sinusoidal steady state, replace L with jωL and C with 1/(jωC). Keep peak, peak-to-peak, and rms values consistent; power formulas use rms.
- A Thévenin equivalent is found from the open-circuit voltage and the resistance seen with independent sources zeroed. Controlled sources must remain active.
- For a first-order RC circuit, τ = RC; the time constant sets the 63.2% step response point and the −3 dB corner at f = 1/(2πRC).
Analog electronics
- An ideal op-amp in negative feedback enforces v+ = v− and zero input current. Check the output against the supply rails before trusting the linear result.
- A BJT in forward active mode has VBE ≈ 0.7 V, IC = βIB, and VCE > VCE(sat). Always test the active-region assumption after solving.
- A MOSFET in saturation follows ID = ½k′(W/L)(VGS − VTH)²; in triode it behaves more like a voltage-controlled resistor.
- Bode magnitude uses 20 log10|H| for voltage gain; a single pole rolls off at −20 dB/decade and contributes −45° at the corner.
Worked example
A BJT has VCC = 12 V, RB = 470 kΩ from VCC to base, RC = 2.2 kΩ, β = 100, and VBE = 0.7 V, with the emitter grounded. Assume active mode: IB = (12 − 0.7)/470 kΩ = 24.0 µA, so IC = 100 × 24.0 µA = 2.40 mA. Then VCE = 12 − (2.40 mA)(2.2 kΩ) = 12 − 5.28 = 6.72 V. Because 6.72 V is well above saturation, the active-mode assumption is valid.
Traps that cost marks
- Reporting an op-amp output beyond the supply rails, or using the ideal gain when the device is saturated.
- Forgetting to verify BJT or MOSFET operating region after a dc solution.
- Mixing rms and peak amplitudes in power calculations, or dropping the 2 in average power formulas.
- Treating a capacitor’s impedance magnitude as 1/(ωC) but losing the −90° phase.
- Ignoring loading when cascading stages or measuring with a finite-impedance instrument.