Calibration offset register and a don't-care BCD decoder
A bench calibration unit for a thermocouple press-fit station stores its sensor offset in an 8-bit two's complement register: 0x00–0x7F are positive counts and 0xFF–0x80 negative ones. The maintenance screen shows the register in hexadecimal only. The commissioning sheet demands an offset of −37 counts, and the technician keyed 0xA5, which the unit accepted without complaint. Firmware computes the corrected reading with a single 8-bit ADD (sensor_byte + offset_byte); there is no overflow or plausibility check, although the intended window is ±25 counts. Elsewhere on the same board, a 4-bit BCD thumbwheel sets the batch size and its four contact lines drive a two-level NAND decoder whose output sinks the 'batch above 5' lamp. The original Karnaugh simplification used codes 1010–1111 as don't-cares, on the argument that the thumbwheel can only produce 0–9. The contacts break before make, so intermediate codes such as 1111 or 1011 sit on the lines for 1–3 ms while the operator turns the wheel. Two complaints are open: the corrected temperature collapses to a large negative value near the top of the sensor range, and the lamp blinks when the wheel is turned down from 9 to 0.
1. Convert −37 to 8-bit two's complement and determine what the technician actually programmed by entering 0xA5. Show the arithmetic and the decimal offset the unit is really applying.
Read the worked answer
Magnitude: 37 = 0010 0101. Invert the bits: 1101 1010. Add 1: 1101 1011 = 0xDB. So the correct entry for −37 is 0xDB, and the shortcut 256 − 37 = 219 = 0xDB confirms it.
Now decode 0xA5 = 1010 0101. The MSB is 1, so it is negative. Invert and add one: 0101 1010 + 1 = 0101 1011 = 91, therefore 0xA5 represents −91 (equivalently 165 − 256 = −91).
The unit is therefore applying an offset of −91 counts instead of −37, i.e. 54 counts too far negative. That alone explains a corrected reading that collapses near the top of the sensor range, because the offset is subtracted at every point of the scale. Note also that the entry is numerically legal as an 8-bit two's complement byte, so no amount of range checking on 0x00–0xFF would have caught it; only a check against the ±25 plausibility specification would have rejected both −91 and the correct −37.
2. The sensor outputs 0x7A and the offset byte is 0x12. Compute the result of the 8-bit addition, explain what the display shows, and state how the firmware should have detected and handled this.
Read the worked answer
0x7A = 122 and 0x12 = 18; the true sum is 140, which does not fit in a signed 8-bit register (maximum +127).
The 8-bit ADD produces 140 − 256 = −116, i.e. 0x8C. Decoding 0x8C as two's complement: 0111 0011 + 1 = 0111 0100 = 116, so the display shows −116 counts for a reading that should be +140 - a sign flip, not a small rounding error.
Detection: signed overflow occurs when both operands have the same sign and the result has the opposite sign. In hardware the 8051 PSW overflow flag is exactly this: V = C6 ⊕ C7 (carry out of bit 6 exclusive-ORed with carry out of bit 7). In C on an 8-bit type the same test must be written explicitly, because plain int promotion hides it.
Handling: the proper fix is to widen the arithmetic to 16 bits with sign extension (0x007A + 0x0012 = 0x008C = 140), or to saturate at +127 and raise a fault. Saturating an 8-bit accumulator is acceptable here only because the specified offset window is ±25; widening is safer and costs one byte of RAM.
3. For the thumbwheel decoder, derive the minimal expression using 1010–1111 as don't-cares, then judge whether that expression is safe in this application. Give a concrete alternative.
Read the worked answer
Let the digit be ABCD with A the MSB. Ones are required at 0110, 0111, 1000, 1001; 1010–1111 are don't-cares. The don't-cares group with the A = 1 cells to give a 4-cell block, so the minimal cover is F = A + BC: one inverter, one 2-input AND, one OR (or three NAND gates).
Safety: the simplification is only valid if the don't-care codes can never occur. Here they do occur. The make-before-break contacts put 1010–1111 on the lines for 1–3 ms during a change, and every one of those codes has A = 1, so F = 1. Turning from 9 (F = 1) to 0 (F = 0) drives the lamp high again for the duration of the transition - exactly the reported blink. Power-up can produce the same codes.
Rule: don't-cares are a statement about the input space, not about the logic. Any human-operated or mechanical input must be assumed able to produce every code.
Alternative: compile the decoder with 1010–1111 forced to 0. The map then gives F = AB' + A'BC, two product terms instead of one block - one extra gate. Cheaper still, and more robust: strobe the decode with a 5 ms monostable after the contacts settle, or replace the BCD wheel with a Gray-coded switch so only one line changes at a time.