Pancyprian TS Dig. Electronics II common mistakes
Pancyprian TS Dig. Electronics II · Understand the traps and how to avoid them.
When converting a signed binary number to decimal, the candidate treats the MSB as an ordinary place value (e.g. reading 1001 as 9) instead of applying two's complement or sign-magnitude interpretation.
The candidate has practised mostly unsigned conversions, so the place-value reflex (8+1=9) overrides the sign rule; the MSB's dual role as sign bit is memorised as a label rather than as a weighted value of -2^(n-1).
What to do instead
Before converting, always ask: is this number declared signed? If yes, compute the value as -b(n-1)*2^(n-1) + sum of remaining bits, then verify by negating and adding: for 1001, invert to 0110, add 1 to get 0111 = 7, so the value is -7. Drill five signed and five unsigned conversions of the same bit pattern side by side until the distinction is automatic.
The candidate simplifies a Boolean expression and silently drops a term or a literal, producing a function that agrees with the original on the tested input but not on all inputs.
Simplification is done by pattern-matching to remembered identities rather than by algebraic derivation, and the candidate never checks the result against the truth table, so an absorbed or mis-copied literal goes unnoticed.
What to do instead
After every simplification, rebuild the truth table of the simplified expression and compare it row by row with the original, or evaluate both at the minterms the dropped term covered. Use Karnaugh maps for up to four variables so each grouping is visible, and write the consensus term explicitly before removing anything.
The candidate draws or analyses a combinational circuit with a NAND or NOR gate but applies AND/OR intuition, for example assuming a NAND output goes high only when all inputs are high.
De Morgan's theorem is known as a formula but not internalised as a behaviour, and the inverting bubble is treated as decoration rather than as a logic inversion applied to the whole gate output.
What to do instead
For every NAND or NOR gate, first write the intermediate node as the complement of the AND (or OR) of its inputs, then push the inversion through with De Morgan before continuing. Practise by converting one circuit between all-NAND and AND/OR/NOT forms and confirming identical truth tables.
When designing a synchronous counter or state machine, the candidate connects flip-flop outputs directly to the next stage's clock inputs (ripple style) while claiming the design is synchronous, or forgets to derive the next-state logic for each flip-flop input.
Ripple counters are simpler to draw and are the first counters learned, so the candidate reproduces the wiring pattern without checking the specification, and excitation tables are skipped because they require extra steps.
What to do instead
State explicitly in the solution whether the design is synchronous or asynchronous. For synchronous designs, tie all clock inputs to one clock and produce a next-state table, then use the flip-flop excitation table (JK or D) to derive each J, K or D input as a function of present state. Verify by simulating the state sequence for at least one full cycle, including the unused states.
The candidate confuses ROM, PROM, EPROM, EEPROM and flash, or treats a PAL as if it had a programmable AND array and a programmable OR array, when in fact a PAL has a fixed OR array.
The device names are memorised as a list without the programming mechanism or array structure attached, and the distinction between programmable and fixed planes is easy to blur when only the acronym is recalled.
What to do instead
Build a comparison table with columns for programmable AND plane, programmable OR plane, erasability and typical use: PROM has a fixed AND array and programmable OR array; PAL has programmable AND and fixed OR; PLA has both programmable; EPROM is UV-erasable, EEPROM and flash are electrically erasable. Recall the table before answering any device-selection question.
The candidate computes the output of a DAC or the digital output of an ADC without accounting for resolution and quantisation, for example treating an 8-bit converter as if it had 256 equal steps between 0 and full scale inclusive, or ignoring the half-LSB quantisation error.
The formula is remembered as 2^n steps but the endpoint convention and the difference between step size and error are not, and candidates substitute numbers into whichever formula comes to mind.
What to do instead
Fix the conventions: an n-bit converter has 2^n codes, the LSB size is V_FS/(2^n - 1) when full scale is the maximum code, and quantisation error is at most plus or minus half an LSB. For a DAC output, compute code times LSB size; for an ADC input, compute the code as the rounded ratio of input to LSB size. Work one numerical example end to end and sanity-check that the maximum code maps to full scale.
The candidate describes a microcontroller program or peripheral configuration without distinguishing memory-mapped I/O registers from ordinary RAM, or assumes a port pin is an output without configuring the direction register.
Programming is learned at a high level where the hardware configuration is hidden, so the candidate writes to a port data register and expects the pin to drive, forgetting that the data-direction and alternate-function registers must be set first.
What to do instead
For every peripheral question, state the initialisation sequence explicitly: enable the peripheral clock, set the direction or mode register, then write or read the data register. Note whether the architecture uses memory-mapped or separately addressed I/O, and check the pin's alternate-function setting before assuming a GPIO function.
When reading a timing diagram or measuring with an oscilloscope, the candidate reports a frequency or duty cycle without confirming the time-base setting, probe attenuation, or trigger, and misreads the period from the wrong part of the waveform.
The measurement is treated as a single number read off the screen rather than as a chain of scale factors, and the candidate does not verify that the displayed waveform is stable and correctly scaled.
What to do instead
Record the time-base (seconds per division), probe attenuation (1x or 10x) and vertical scale before quoting any value, then compute period as divisions times time-base and frequency as its reciprocal. Confirm the trigger is stable and the probe is compensated; cross-check against a known reference signal such as the oscilloscope's calibration output.
When a digital circuit misbehaves, the candidate immediately replaces ICs or rewrites code instead of first checking supply voltage, ground continuity, and floating or unconnected inputs.
Troubleshooting is approached as component substitution because that is the fastest action available, and the candidate has not internalised that an unconnected CMOS input can float to an indeterminate level and cause erratic behaviour.
What to do instead
Follow a fixed order: verify supply and ground at the IC pins, check that every unused input is tied high or low, then probe signal levels at each stage from input to output. Only after these checks should a component be suspected. Document the measured values at each node so the first deviation from expected logic levels identifies the faulty stage.
The candidate writes a hexadecimal or binary value into a register or memory location with the wrong bit width, dropping leading zeros or truncating, and then reports a result that is off by a factor of 16 or 256.
Conversions are done digit by digit without tracking the width of the destination, and leading zeros are treated as insignificant even though they carry positional weight in a fixed-width field.
What to do instead
Always annotate the bit width before converting: group binary into nibbles from the right, pad with leading zeros to the declared width, and convert each nibble to one hex digit. After conversion, convert back to binary and compare with the original bit pattern, confirming the number of digits matches the register width.