Pancyprian TS Dig. Electronics II cheat sheet

Positional value: in base b, digit d at position i (counting from 0 at the radix point) contributes d·b^i; 1101₂ = 8+4+1 = 13₁₀.

Binary→hex: group bits in fours from the radix point; binary→octal: group in threes; pad with zeros outward, never inward.

Signed representations: sign-magnitude, 1's complement (invert bits), 2's complement (invert then add 1); 2's complement is preferred because it gives one zero and a single adder circuit.

n-bit 2's complement range: −2^(n−1) to +2^(n−1)−1; negate by inverting all bits and adding 1, including the sign bit.

BCD encodes each decimal digit in 4 bits (0–9); codes 1010–1111 are invalid, so BCD addition needs a +6 correction whenever a nibble exceeds 9 or a carry leaves it.

Gray code changes exactly one bit between adjacent codes; binary→Gray: g_i = b_i XOR b_(i+1), with the MSB copied unchanged.

Boolean identities: A+A·B = A (absorption), A+A'B = A+B, A·(A+B) = A, (A+B)' = A'·B' and (A·B)' = A'+B' (De Morgan).

Canonical forms: minterm = product term with every variable (SOP, Σm); maxterm = sum term with every variable (POS, ΠM); Σm equals the ΠM of the missing indices.

Karnaugh grouping rules: groups of 1, 2, 4, 8 cells; wrap across edges; largest possible groups; overlap allowed; each group yields a product term with variables that stay constant.

Universal gates: NAND and NOR each implement NOT, AND, OR alone; NAND is preferred in CMOS because it is faster and smaller than AND.

XOR is 1 for an odd number of 1 inputs; XNOR is 1 for even parity; A⊕B = A·B' + A'·B and A⊕B⊕C is a 3-bit odd-parity function.

NAND-only conversion: NOT = NAND with inputs tied; AND = NAND followed by NAND-inverter; OR = invert both inputs then NAND (bubble pushing).

Half adder: S = A⊕B, C = A·B. Full adder: S = A⊕B⊕Cin, Cout = A·B + Cin·(A⊕B); a full adder can be built from two half adders plus an OR gate.

Ripple-carry adder delay grows linearly with bit width; carry-lookahead computes generate G = A·B and propagate P = A⊕B to reduce delay to roughly logarithmic.

Multiplexer: 2^n data inputs, n select lines, 1 output; a 2^n:1 MUX with n select lines implements any n-variable function by tying data inputs to 0 or 1.

Decoder: n inputs, 2^n outputs, exactly one active; a 3-to-8 decoder with active-low outputs plus NAND gates implements any 3-variable SOP directly.

Static-1 hazard: two product terms differing in one literal (e.g. A·B + A'·C) can glitch on that variable; add a consensus term (B·C) to remove it.

Active-low signals and bubble notation: a bubble on an output means the pin asserts low; mixed-logic symbols let you read the Boolean function directly from the schematic.

Latch vs flip-flop: a latch is level-sensitive (transparent while enable is high); an edge-triggered flip-flop samples only at the clock edge.

Characteristic equations: D: Q⁺ = D; T: Q⁺ = T⊕Q; JK: Q⁺ = J·Q' + K'·Q; SR: Q⁺ = S + R'·Q with S·R = 0 forbidden.

JK flip-flop with J = K = 1 toggles on every clock edge; with J = K = 0 it holds; this makes JK ideal for ripple and synchronous counters.

Setup time t_su is the interval data must be stable before the clock edge; hold time t_h is the interval after it; violating either causes metastability.

Maximum clock frequency: T_clk ≥ t_cq + t_comb + t_su; the critical path is the longest combinational delay between two registers.

Asynchronous (ripple) counter: each stage clocks the next from the previous Q, so delays accumulate and transient decoded states appear; synchronous counters clock all stages together.

Modulo-N counter needs ceil(log2 N) flip-flops; unused states in a truncated sequence must be forced back with reset or self-correcting logic.

Shift register modes: SISO, SIPO, PISO, PIPO; a ring counter recirculates one bit, a Johnson counter inverts the feedback giving 2n states for n stages.

Mealy output depends on state and input (can glitch); Moore output depends only on state (glitch-free but one cycle later); state diagrams label edges input/output.

Capacity = 2^address_lines × data_width; a 1K×8 RAM holds 1024 bytes and needs 10 address lines and 8 data lines.

Address decoding: for a block of size 2^k starting at address A, the upper address bits above k select the chip; unused lines go to the chip-enable decoder.

RAM is volatile (SRAM uses 6-transistor cells, fast, no refresh; DRAM uses 1 transistor + capacitor, needs refresh); ROM is non-volatile and factory- or mask-programmed.

PROM is one-time programmable (fuses/antifuses), EPROM is UV-erasable, EEPROM is electrically erasable per byte, and flash erases in blocks.

Access-time parameters: t_AA (address access), t_CE (chip enable), t_OE (output enable); the system cycle must exceed the slowest of these.

PROM as a logic device: n inputs give 2^n product terms (fixed AND array), and the programmable OR array stores the SOP function.

PAL/PLA: PLA has both programmable AND and OR arrays; PAL has a fixed AND array and programmable OR array; CPLD/FPGA use LUTs and macrocells.

Memory expansion: to widen, place chips in parallel sharing address lines and splitting data lines; to deepen, decode additional address lines into separate chip enables.

Tri-state outputs allow many memory or peripheral devices on one data bus; only the enabled device drives the bus, all others must be high-Z.

n-bit DAC resolution (LSB step) = V_FS / (2^n − 1); output = V_ref · D / 2^n for a binary-weighted or R-2R ladder DAC.

R-2R ladder uses only two resistor values, so it is preferred in ICs; binary-weighted resistors need precise ratio-matched values across a wide range.

DAC specs: resolution (bits), settling time, monotonicity (output never decreases as code increases), DNL and INL in LSBs.

Quantization error of an ideal n-bit ADC is ±½ LSB = ±V_FS / (2^(n+1)); SNR(dB) ≈ 6.02n + 1.76 for a full-scale sine input.

Flash ADC uses 2^n − 1 comparators in one step (fastest, lowest resolution); SAR uses a DAC and comparator over n cycles; dual-slope integrates and is accurate but slow.

Sample-and-hold is required because the ADC input must stay constant during conversion; the sampling switch must be fast enough for the hold capacitor to settle.

Nyquist criterion: f_s ≥ 2·f_max; otherwise aliasing folds high frequencies into the baseband, which an anti-aliasing low-pass filter placed before the sampler prevents.

Successive-approximation search: test MSB first, keep the bit if the DAC output ≤ input, then proceed down; n comparisons produce the n-bit result.

ADC figures of merit: conversion time, throughput (samples/s), ENOB, missing codes; a monotonic DAC guarantees no missing codes in the associated SAR ADC.

Von Neumann shares one memory space and bus for code and data; Harvard uses separate program and data memories and buses, allowing simultaneous fetch and data access.

CISC has many variable-length instructions and microcode; RISC has fixed-length instructions, load/store architecture, and a large register file.

MCU building blocks: CPU core, program flash, SRAM, GPIO ports, timers/counters, UART/SPI/I²C, ADC, interrupt controller, clock and watchdog.

Memory-mapped I/O: peripherals appear as addresses, so ordinary load/store instructions access control and data registers.

Interrupt sequence: finish current instruction, save context (PC, flags), jump to vector, run ISR, restore context, return; the ISR must clear the source flag.

Stack is LIFO and grows downward in many architectures; subroutine call pushes the return address, return pops it; unbalanced push/pop corrupts execution.

Addressing modes: immediate, direct, indirect, indexed, register; the effective address calculation determines operand fetch cost.

Polling versus interrupt: polling wastes CPU cycles and can miss events; interrupts respond quickly but need latency and priority handling.

Watchdog timer must be refreshed inside the main loop; if the program hangs, the watchdog resets the MCU, restoring known state.

Oscilloscope probe: use ×10 for high impedance and low loading; compensate the probe against the calibrator square wave before measuring.

Bandwidth rule: scope and probe bandwidth should be at least 5× the highest signal frequency to keep rise-time error small; t_r ≈ 0.35/BW.

Logic analyzer triggers on patterns and protocols; a scope shows analog quality (ringing, overshoot, slow edges); choose by the question asked.

Stuck-at fault: a node fixed at 0 or 1; trace with a logic probe from the output backward to find where the expected toggling stops.

Floating CMOS input drifts and causes excess supply current and oscillation; tie unused inputs to V_CC or ground through a resistor.

Power-rail checks: measure V_CC at the IC pin, not at the supply; decoupling capacitors (typically 100 nF per IC) must sit close to the pin.

Clock troubleshooting: verify frequency, duty cycle and edge quality; a missing clock freezes counters, a slow edge causes double-clocking.

Propagation delay budget: total = sum of gate delays along the path; compare with the clock period to check setup-time margin.

Grounding and noise: use a short ground lead, avoid ground loops, and separate digital return currents from analog ones in mixed-signal boards.