Pancyprian TS Dig. Electronics II key terms

A binary representation of signed integers in which the most significant bit carries negative weight; the negative of a number is formed by inverting all bits and adding one. It allows subtraction to be performed with ordinary addition circuits.

The leftmost bit of a signed binary word, which indicates polarity rather than magnitude. In two's complement a 1 means the value is negative, and the remaining bits encode the magnitude in complemented form.

An error condition in fixed-width signed arithmetic occurring when a result falls outside the representable range. It is detected when the carry into and the carry out of the sign bit differ.

A status bit set by an arithmetic unit when a carry out of, or borrow into, the most significant bit occurs. It supports multi-word addition and unsigned magnitude comparison.

Binary-coded decimal, a code in which each decimal digit is stored in its own four-bit group. It simplifies display driving and decimal input, but arithmetic requires correction because six of the sixteen code words are invalid.

A binary code in which consecutive values differ in exactly one bit position. It reduces spurious output combinations during transitions and is widely used in rotary encoders and Karnaugh map ordering.

The number of bit positions in which two equal-length code words differ. It measures a code's ability to detect and correct errors, since a distance of d allows detection of up to d minus one bit errors.

An extra bit appended to a data word so that the total number of ones is even or odd. It detects any single-bit error but cannot locate or correct it.

Two Boolean identities stating that the complement of a sum equals the product of the complements, and the complement of a product equals the sum of the complements. They allow any expression to be converted between AND-OR and OR-AND forms.

A Boolean expression written as the OR of minterms, one for each input combination producing a logic one. Each minterm is a product containing every variable in true or complemented form.

A product term containing every variable of a function exactly once, in either true or complemented form. It corresponds to a single row of the truth table and to one cell of a Karnaugh map.

A rectangular diagram arranging truth-table cells so that adjacent cells differ in one variable. Grouping adjacent ones in powers of two yields a minimised sum-of-products expression without algebraic manipulation.

An input combination whose output value is irrelevant because it never occurs in normal operation. Such entries may be treated as 0 or 1 to enlarge groupings and simplify the resulting expression.

A logic gate whose output is the complement of the AND of its inputs. Because it is functionally complete, any combinational function can be built from NAND gates alone.

A logic gate whose output is the complement of the OR of its inputs. Like the NAND gate it is functionally complete, and it is the natural building block in some bipolar logic families.

A two-input gate whose output is one when the inputs differ and zero when they are equal. It implements modulo-two addition and forms the core of parity generators and comparators.

A combinational circuit that adds two single bits, producing a sum and a carry output. It cannot accept an incoming carry, so it is combined with full adders to build multi-bit adders.

A combinational circuit adding three single bits: two operands and a carry input. It outputs a sum and a carry, and cascading several stages forms a multi-bit binary adder.

A multi-bit adder built from full adders connected in series so that each carry propagates to the next stage. It is simple and compact but slow, because the final sum waits for the carry chain.

A combinational device that selects one of several data inputs and routes it to a single output under the control of select lines. It can also implement arbitrary Boolean functions when inputs are tied to constants.

A combinational circuit that converts an n-bit binary input into one active output line out of two to the n possible lines. It is used for address selection, memory chip enabling and seven-segment display driving.

A transient incorrect output in combinational logic caused by unequal propagation delays along different paths when an input changes. Static hazards appear as brief glitches and are removed with redundant consensus terms.

The time between a change at a gate input and the resulting stable change at its output. It limits maximum operating frequency and causes timing hazards and races in digital circuits.

The minimum interval before the active clock edge during which a flip-flop's data input must remain stable. Violating it can cause metastability or capture of an incorrect value.

The minimum interval after the active clock edge during which the data input must remain stable. Together with setup time it defines the valid timing window for reliable flip-flop operation.

An unstable state in which a flip-flop output hovers between logic levels after a timing violation. It resolves randomly after some delay, so synchronisers are used when sampling asynchronous signals.

A clocked storage element that copies its data input to the output at the active clock edge. It is the standard building block for registers, shift registers and synchronous counters.

A cascade of flip-flops in which each stage passes its content to the next on every clock pulse. It converts serial data to parallel form and back, and can implement delay lines.

A shift register whose output is fed back to its input so that a single one circulates through the stages. It produces a sequence of non-overlapping timing pulses without decoding logic.

A shift register with inverted feedback, producing a sequence of length twice the number of stages. It gives more states than a ring counter but requires simple decoding.

A counter in which each stage is clocked by the output of the preceding stage rather than by a common clock. It is simple but accumulates propagation delays and produces transient decoding glitches.

A counter in which all flip-flops receive the same clock and change simultaneously. It avoids ripple delay and decoding glitches at the cost of more combinational logic.

Static random-access memory storing each bit in a bistable latch of six transistors. It is fast and needs no refresh, but its cell is large, so it is used mainly for caches and small buffers.

Dynamic random-access memory storing each bit as charge on a capacitor with a single access transistor. It is dense and cheap but must be periodically refreshed because the charge leaks away.

Non-volatile memory that stores data as charge on floating gates and is erased in blocks rather than byte by byte. It retains contents without power and is common in microcontrollers and storage cards.

Electrically erasable programmable read-only memory that can be written and erased byte by byte in circuit. It suits small non-volatile parameter storage, though write endurance and speed are limited.

Programmable logic device whose internal AND-OR array can be configured by the user to realise custom combinational functions. Variants differ in whether the AND array, OR array or both are programmable.

Field-programmable gate array, an integrated circuit of configurable logic blocks and routing that the designer programs to implement a digital system. Configuration is usually held in SRAM and loaded at power-up.

The smallest analogue change a converter can distinguish, equal to full-scale range divided by two to the n for an n-bit converter. It is often expressed in volts per least significant bit.

The difference between the true analogue value and the nearest digital code, bounded by half a least significant bit. It is inherent in digitisation and appears as noise in the reconstructed signal.

A circuit that captures an analogue voltage on a capacitor and holds it steady while the converter digitises it. It prevents conversion errors caused by a rapidly changing input during conversion.

The folding of high-frequency components into lower frequencies when a signal is sampled below twice its highest frequency. An anti-aliasing low-pass filter before the converter prevents it.

A resistor network using only two resistance values to produce binary-weighted currents for digital-to-analogue conversion. It is easier to fabricate accurately than a network of many binary-weighted resistors.

An analogue-to-digital conversion method that tests bits from most to least significant, comparing the input against a DAC output each step. It gives good speed and resolution at moderate cost.

An addressing scheme in which peripheral registers occupy the same address space as memory and are accessed with ordinary load and store instructions. It simplifies programming but consumes address space.

A signal that suspends the current program, runs a dedicated service routine and then resumes execution. It allows a processor to respond promptly to external events without polling.

A table of addresses telling the processor where each interrupt service routine begins. Its location is fixed by the architecture, and each source has a defined entry.

A register holding the address of the top of the stack, the area where return addresses and saved registers are stored. It is updated automatically on push and pop operations.

A register containing the address of the next instruction to be fetched. It increments automatically during sequential execution and is loaded with a new value by jumps and calls.

The sequence of fetch, decode and execute steps by which a processor runs one instruction. Its duration, multiplied by the clock period, determines program execution time.

An instrument displaying voltage against time on a screen. It is used to inspect waveforms, measure amplitude, period, rise time and noise, and to check clock and data signals.

An instrument that captures many digital channels simultaneously and displays them as timing diagrams. It is used to decode buses and diagnose state sequences that an oscilloscope cannot easily show.

Adjustment of a scope probe's trimmer capacitor so that it matches the input capacitance of the oscilloscope. Correct compensation prevents distorted pulse edges and inaccurate amplitude readings.

The return connection of a scope probe, which must be attached to circuit ground. A long or missing ground lead adds inductance and causes ringing or misleading waveforms on fast edges.

A logic gate input connected to neither a defined high nor low level. It picks up noise and causes erratic switching, so unused inputs must be tied to a supply rail or a defined level.

A resistor connecting an input or open-drain output to the positive supply so that it defaults to a logic high. It is released to that level when the driving device turns off.

A small capacitor placed close to each integrated circuit between supply and ground to supply transient currents. It reduces supply noise and prevents false switching caused by current spikes.

A momentary rise in a circuit's local ground potential caused by fast current surges through lead inductance. It can cause false logic levels and erratic behaviour in high-speed switching circuits.