Pancyprian TS Dig. Electronics II study plan
Pancyprian TS Dig. Electronics II · Give each week a clear focus.
8 weeks · About 6 hours per week
Number systems, binary codes and Boolean algebra & Logic gates and combinational logic design
Convert numbers between binary, octal, decimal and hexadecimal without a calculator, and justify each step in writing
Derive the truth table, canonical SOP and POS forms for any 3-variable Boolean function given in words
Apply Karnaugh-map minimisation to 4-variable functions including don't-care conditions, and prove the result is minimal
State and apply De Morgan's laws and the consensus theorem to simplify expressions algebraically
Implement a given simplified expression using only NAND gates or only NOR gates
Your checkpoint
A worked problem set of 20 minimisation exercises (10 K-map, 10 algebraic) with full derivations, self-marked against truth-table verification
Logic gates and combinational logic design
Design a combinational circuit from a word problem: truth table, minimisation, gate-level schematic
Build and analyse a full adder and a 4-bit ripple-carry adder, identifying the carry propagation path
Explain and design a 4-to-1 multiplexer and use it to implement an arbitrary 3-variable function
Design a 2-to-4 decoder with enable and explain how it realises minterms
Identify and eliminate static-1 and static-0 hazards in a two-level AND-OR implementation
Your checkpoint
A design portfolio of 5 combinational circuits (adder, comparator, mux-based function, decoder-based function, hazard-free version) each with truth table, minimised equations and gate schematic
Sequential logic: flip-flops, registers and counters
Compare SR, JK, D and T flip-flops by excitation table, characteristic equation and timing behaviour
Convert one flip-flop type into another and verify the conversion with a state table
Derive the next-state equations for a synchronous counter from its state diagram
Distinguish synchronous from asynchronous counters and predict ripple-counter timing skew
Draw a timing diagram for a given clocked circuit including setup and hold constraints
Your checkpoint
A written comparison sheet plus three complete sequential designs (mod-6 synchronous counter, 4-bit shift register with parallel load, sequence detector) with state diagrams, state tables, next-state equations and timing diagrams
Sequential logic: flip-flops, registers and counters & Memory devices and programmable logic
Design a mod-N counter for arbitrary N using both reset and preset techniques and state the trade-offs
Explain the internal organisation of SRAM, DRAM, ROM, PROM, EPROM and EEPROM cells and their relative density and volatility
Compute the address and data line counts for a given memory capacity and word width
Design a memory map that places two or three chips at specified addresses using decoders and chip-select logic
Describe how a PAL, PLA and CPLD differ in programmable AND/OR arrays and give one use case for each
Your checkpoint
A memory-subsystem design report: address map table, chip-select decoding schematic, capacity calculations, and a one-page comparison table of memory and PLD technologies
Memory devices and programmable logic & Digital-to-analog and analog-to-digital conversion
Compute resolution, full-scale range and quantisation error for a given DAC or ADC specification
Analyse an R-2R ladder DAC and calculate its output for a given digital input
Compare flash, successive-approximation, dual-slope and sigma-delta ADC architectures by speed, resolution and cost
Calculate the minimum sampling rate for a signal and explain aliasing and the role of the anti-aliasing filter
Interpret DAC/ADC datasheet parameters including INL, DNL, settling time and SNR
Your checkpoint
A conversion workbook: 10 numerical problems on resolution, sampling and R-2R outputs, plus a one-page architecture selection guide mapping four application scenarios to a justified ADC/DAC choice
Microcontrollers and microprocessor fundamentals
Describe the von Neumann fetch-decode-execute cycle and identify the role of PC, IR, MAR, MDR and the ALU
Distinguish von Neumann from Harvard architecture and explain the implications for a microcontroller
Explain memory-mapped I/O and compare polling, interrupt-driven and DMA transfer
Trace a short assembly program instruction by instruction, tracking registers and flags
Map the main blocks of a typical 8-bit microcontroller: CPU core, Flash, RAM, GPIO ports, timers, serial interface and ADC
Your checkpoint
A hand-traced execution log of a 15-instruction assembly routine showing register, flag and memory state after every instruction, plus an annotated block diagram of an 8-bit microcontroller
Digital circuit measurements, troubleshooting and laboratory practice & Microcontrollers and microprocessor fundamentals
Use an oscilloscope correctly: probe compensation, triggering, timebase and vertical scaling, and read setup/hold timing from a captured waveform
Apply a systematic fault-finding procedure (observe, hypothesise, isolate, confirm) to a combinational and a sequential circuit
Distinguish stuck-at, open-circuit, bridging and race faults by their observable symptoms
Explain debouncing, pull-up/pull-down resistors, fan-out limits and decoupling in practical logic and microcontroller circuits
Describe how a logic analyser is used to capture a serial bus transaction and decode it
Your checkpoint
A troubleshooting casebook of 6 documented faults: symptom description, measurement performed, root cause and fix, each written as a short laboratory report
Number systems, binary codes and Boolean algebra & Logic gates and combinational logic design & Sequential logic: flip-flops, registers and counters & Memory devices and programmable logic & Digital-to-analog and analog-to-digital conversion & Microcontrollers and microprocessor fundamentals & Digital circuit measurements, troubleshooting and laboratory practice
Complete two full timed mock papers under exam conditions and score them against a mark scheme
Re-derive from memory the key formulas: resolution, memory capacity, counter modulus, K-map rules and setup/hold
Diagnose and repair the three weakest areas identified in the mock results
Produce a one-page formula and definitions sheet covering all seven domains
Explain aloud the solution to one mixed-domain problem per domain to confirm understanding
Your checkpoint
Two completed timed mock papers with self-marking, a corrected error log listing every mistake and its cause, and a final one-page formula sheet
Milestones
Week 2: Can minimise any 4-variable function by K-map and design a working combinational circuit from a word problem without notes, scoring at least 80% on the week 2 portfolio
Week 4: Can draw a state diagram, derive next-state equations and produce a correct timing diagram for a mod-N counter in under 25 minutes, and can compute memory capacity and address decoding without reference material
Week 6: Scores at least 70% on a self-made 20-question test covering domains 1 to 5, and can hand-trace an assembly routine correctly tracking registers and flags
Week 8: Scores at least 75% on both timed mock papers with no domain below 60%, and the error log shows every recurring mistake has been reworked and re-verified