Pancyprian TS Dig. Electronics II flashcards

33 cards. Read the term and the definition here. The deck at the top of this page is optional.

2's complement range

For n bits, representable values run from −2^(n−1) to +2^(n−1)−1. Negation inverts every bit and adds one; one zero exists, so subtraction uses the same adder as addition.

BCD correction

After adding two BCD digits, if the nibble result exceeds 9 or a carry leaves the nibble, add 6 to skip the six invalid codes 1010 through 1111 and restore valid decimal coding.

De Morgan's theorems

The complement of a product equals the sum of the complements, and the complement of a sum equals the product of the complements: (A·B)' = A'+B' and (A+B)' = A'·B'.

Karnaugh map grouping

Combine adjacent 1-cells in groups of 1, 2, 4, 8 or 16, wrapping across edges. Each group yields a product term containing only variables that stay constant inside the group.

Minterm versus maxterm

A minterm is an AND term containing every variable, giving 1 for one input combination. A maxterm is an OR term containing every variable, giving 0 for one combination.

Universal gates

NAND and NOR are universal because each can build NOT, AND and OR alone. Tie both inputs for NOT; NAND is preferred in CMOS for speed and smaller area.

Full adder equations

Sum equals A XOR B XOR Cin, and carry-out equals A·B plus Cin·(A XOR B). Two half adders plus an OR gate form one full adder.

Multiplexer as function generator

A 2^n-to-1 multiplexer with n select lines implements any n-variable Boolean function when each data input is tied to 0 or 1 according to the truth table.

Static-1 hazard

Two product terms differing in one literal can produce a glitch when that variable changes. Adding the consensus term removes the hazard in two-level sum-of-products logic.

Decoder implementation

An n-to-2^n decoder activates exactly one output per input code. With active-low outputs, NAND gates combine those outputs to realize any sum-of-products expression directly.

Latch versus flip-flop

A latch is level-sensitive and transparent while enabled. An edge-triggered flip-flop samples its input only at the clock transition, which prevents race-through in synchronous designs.

JK flip-flop behavior

With J and K both high, the output toggles on each clock edge; both low holds; J high alone sets; K high alone resets. It removes the forbidden state of SR.

Setup and hold time

Setup time is how long data must be stable before the clock edge; hold time is how long after. Violation causes metastability, where the output is unpredictable for an indefinite interval.

Maximum clock frequency

The clock period must be at least register clock-to-output delay plus the longest combinational path plus setup time. That critical path sets the maximum operating frequency.

Ripple versus synchronous counter

A ripple counter clocks each stage from the previous output, so delays accumulate and transient states appear. A synchronous counter clocks all stages together, giving clean decoded states.

Johnson counter states

An n-stage shift register with inverted feedback recirculates a pattern of n zeros then n ones, producing 2n distinct states and a naturally decoded output.

Memory capacity formula

Capacity equals 2 raised to the number of address lines, multiplied by data width in bits. A 1K×8 device therefore needs 10 address lines and holds 1024 bytes.

SRAM versus DRAM

SRAM stores a bit in a six-transistor cell and needs no refresh, so it is fast but bulky. DRAM uses one transistor and a capacitor and must be refreshed periodically.

PROM as logic array

A PROM has a fixed AND array producing all 2^n product terms and a programmable OR array. It stores sum-of-products functions by choosing which product terms are summed.

Tri-state bus

Tri-state outputs can be high, low, or high impedance. Only one enabled driver may drive a shared data bus; all others must be in the high-impedance state.

DAC resolution

The LSB step equals full-scale voltage divided by 2^n minus one. Output equals reference voltage times the digital code divided by 2^n for an ideal converter.

R-2R ladder advantage

The R-2R ladder needs only two resistor values, so matching is easier in integrated circuits. Binary-weighted DACs need precise ratios across a wide range of resistor values.

Quantization error

An ideal n-bit converter has maximum quantization error of half an LSB, that is full-scale divided by 2^(n+1). The signal-to-noise ratio is about 6.02n + 1.76 dB.

Nyquist sampling criterion

Sampling frequency must be at least twice the highest input frequency. Otherwise aliasing folds high-frequency components into the baseband; an anti-aliasing filter placed before the sampler prevents it.

SAR ADC operation

A successive-approximation converter tests bits from most significant to least, comparing the DAC output with the input. It needs n clock cycles and only one comparator.

Harvard versus von Neumann

Harvard architecture uses separate program and data memory with separate buses, allowing simultaneous instruction fetch and data access. Von Neumann shares one memory space and bus.

Memory-mapped I/O

Peripheral registers are assigned addresses in the same space as memory, so ordinary load and store instructions read and write control and data registers.

Interrupt service routine

On an interrupt the CPU saves context, jumps to the vector, runs the handler, then restores context. The handler must clear the peripheral flag or the interrupt repeats.

Watchdog timer

A counter that resets the processor if the firmware fails to refresh it within the timeout. It recovers the system from a hung loop or runaway code.

Oscilloscope probe loading

A ×10 probe raises input impedance and reduces circuit loading. Compensate it against the scope calibrator square wave so fast edges are not distorted.

Stuck-at fault tracing

A node permanently held at 0 or 1. Use a logic probe or scope to follow the expected toggling signal backward from the faulty output to the first point where it stops.

Floating CMOS input

An unconnected CMOS gate input drifts to an intermediate voltage, causing both transistors to conduct. It produces excess supply current, oscillation, and random logic behavior.

Propagation delay budget

Total path delay is the sum of gate delays plus wiring delay. Comparing it with the clock period minus setup time shows whether timing margin is positive.