Static hazard on a relay-selector enable line
The relay selector of an environmental chamber routes one of eight sensor channels to a chart recorder. A 3-bit channel address from the front-panel selector feeds a decoder built from 74HC00 NAND gates (tpd 9 ns typical at 4.5 V, three levels deep). Its output E must be high for channels 2, 3, 5 and 7, which form a transducer group, and low otherwise. The designer's simplified expression is E = A'B + AC, with A the MSB. E also drives one input of an AND gate that gates a 1 MHz reference clock into a totaliser counter, so any falling edge on E while the clock is high is counted as an event. Whenever the operator steps the selector between channel 3 and channel 7 the totaliser gains one or two counts and the relay chatters. A 100 MHz oscilloscope with a 12 cm ground lead shows a 30–40 ns negative notch on E at the transition; the notch disappears when the probe tip is touched to the gate output with the ground clip removed. Production wants the miscounting stopped without redesigning the front panel.
1. Use a Karnaugh map to confirm which minterms E covers, identify the hazard and the exact input condition that triggers it, and explain physically why the notch appears.
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With A as MSB and C as LSB:
- A'B covers 010 (2) and 011 (3).
- AC covers 101 (5) and 111 (7).
So E = Σm(2,3,5,7), as required. In the map, cells 3 (011) and 7 (111) are adjacent and are covered by different product terms.
The hazard condition is B = C = 1, i.e. the variable A changing between channel 3 and channel 7. Physically, A reaches the A'B gate through an inverter and reaches the AC gate directly, so when A rises the A'B term falls after one inverter delay while AC rises after its own gate delay. For roughly two gate delays (≈ 18 ns, extended by the output stage and the probe) both products are 0 and E dips - a static-1 hazard. Propagation delays are not specified as matched, so the width is not predictable and can grow at temperature extremes or with a different logic family.
The fix is the consensus term BC: E = A'B + AC + BC. It is logically redundant (BC is 1 only where both other terms already give 1), but when B = C = 1 it holds E high regardless of A and of the inverter delay.
2. Give the modified expression and compare adding the consensus gate with registering E in a 74HC74 clocked from the 1 MHz reference. Which do you recommend and why?
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Modified expression: E = A'B + AC + BC. In NAND form that is A → inverter, three product NANDs, a 3-input NAND and an inverter for the OR; about three extra gates and one extra level (~9 ns) of delay on E.
Registering: clock E into a 74HC74 on the 1 MHz reference and use Q as the enable. This removes all glitches, including those the consensus term cannot touch - notably the functional hazard when the operator steps from channel 3 (011) to channel 4 (100), where two address bits change at once and the output can pulse no matter how the terms are grouped. Cost is one clock of latency (1 µs) and one package.
Recommendation: register. The load is a relay driver and a clock gate, both indifferent to 1 µs, and the selector is human-operated, so latency is irrelevant. The consensus term fixes only single-variable changes and must be re-derived every time the channel map changes; the register is insensitive to the map. If the board must stay gate-only, the consensus term is still worthwhile because 3↔7 is the transition the operator makes most often, but it is a partial fix and should be documented as such.
3. The notch disappears when the ground clip is removed. Decide whether the notch is a measurement artefact or a real defect, and describe how you would settle the question.
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It is almost certainly real. A 35 ns notch is far too slow to be a probing artefact: a 12 cm ground lead produces ringing with a period of a few nanoseconds and overshoot, not a 35 ns flat-bottomed pulse. Removing the clip does not improve fidelity - it lengthens the ground return and adds inductance, so artefacts get worse, not better. What the removal probably did is add enough series inductance and capacitance to load and slow the node, or move the probe off the actual gate output.
Independent evidence that it is real: the totaliser gains counts, which requires a genuine falling edge on E while the clock is high. A scope artefact cannot clock a counter.
How to settle it properly:
- Probe with a short spring ground at the gate output pin, and compare against the gate's own input pins to confirm the timing.
- Cross-check with a logic analyser at the same node using its own ground; if both instruments show the pulse at the same address transition, it is in the circuit.
- Predict the width from the datasheet (two to three gate delays at the actual supply voltage and temperature) and compare with the measured 30–40 ns. Agreement at the right order of magnitude is strong confirmation.
- Decisive test: fit the consensus term or the 74HC74, then confirm the totaliser stops gaining counts.