Ten-bit weigh-scale ADC versus a 12-bit upgrade
A weighing platform uses a 10-bit SAR ADC with a 4.096 V reference, sampling the load-cell amplifier output at 1 kSa/s. The analog front end presents 1.2 mV rms of broadband noise, and the amplifier output swings between 0.2 V and 3.9 V over the 3 kg range. A 1.2 kHz switching ripple of about 80 mV peak couples in from the adjacent DC-DC converter. The only filtering is a 1 kΩ/100 nF RC at the ADC pin. The control loop needs a fresh weight value every 5 ms. Marketing has asked for a pin-compatible 12-bit ADC to 'get four times the resolution', and an engineer has proposed averaging 16 samples per reading. The scale must resolve 5 g, and at rest the last displayed digit currently jitters by ±3 counts.
1. Compute the LSB, the quantisation noise, the total input-referred noise and the effective number of bits. Decide whether the 12-bit part delivers the promised improvement.
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LSB = 4.096 V / 1024 = 4.0 mV. Quantisation noise rms = LSB/√12 = 4.0/3.464 = 1.155 mV. Total noise = √(1.2² + 1.155²) = √(1.44 + 1.334) = 1.665 mV rms, about 11 mV peak-to-peak (×6.6), i.e. roughly ±1.4 LSB - which matches the observed ±3-count jitter once display rounding is included.
ENOB = log2(VFS / (noise·√12)) = log2(4.096 / (0.001665 × 3.464)) = log2(710) ≈ 9.5 bits. The 10-bit part is already delivering essentially all the resolution the analog front end allows.
With a 12-bit part: LSB = 1.0 mV, quantisation noise 0.289 mV, total = √(1.2² + 0.289²) = 1.234 mV, ENOB = log2(4.096 / 0.004275) ≈ 9.9 bits. That is about 0.4 bit of real improvement for a more expensive converter.
Conclusion: the upgrade is not justified until the analog noise is reduced. To actually obtain 12 bits the front-end noise must fall below about 0.3 mV rms - a layout, shielding and amplifier problem, not a converter problem. Fix the analog side first, then buy the 12-bit part.
2. Analyse the 1.2 kHz ripple: where does it appear in the sampled data, how much does the existing RC attenuate it, and what do you do about it?
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Sampling at 1 kSa/s, the 1.2 kHz ripple aliases to |1200 − 1000| = 200 Hz. Once aliased it is indistinguishable from a genuine 200 Hz component of the weight signal, and no digital filter can separate them.
The RC corner is fc = 1/(2π × 1 kΩ × 100 nF) ≈ 1.6 kHz, so at 1.2 kHz the attenuation is only 1/√(1 + (1.2/1.6)²) ≈ 1/1.25, i.e. about −2 dB. The 80 mV peak becomes roughly 64 mV peak - sixteen LSBs. The filter is doing nothing useful.
Options, in order of preference:
- Raise the sample rate so the ripple is no longer aliased. At 12 kSa/s the 1.2 kHz ripple stays at 1.2 kHz in the data and can be removed by averaging over an integer number of its periods (10 samples per period, so average 20 samples = exactly two periods).
- Add a proper anti-alias filter - a 2nd-order Sallen-Key at 300 Hz gives about −24 dB at 1.2 kHz, and a 4th-order about −48 dB. Needed attenuation: 80 mV must fall below 4 mV, i.e. 26 dB.
- Attack the source: snubber or re-route the DC-DC, or move the converter.
A single extra RC is not enough here; the required attenuation is 26 dB and one pole at 300 Hz gives only about 12 dB.
3. Given the 5 ms loop deadline and the 5 g resolution requirement, decide whether 16-sample averaging is feasible and state the configuration you would specify.
Read the worked answer
Resolution check: 5 g on 3 kg is one part in 600 of a 3.7 V span ≈ 6.2 mV, about 1.5 LSB of the 10-bit part. So the noise must be averaged down well below one LSB - averaging is mandatory, not optional.
Timing check: 16 samples at 1 kSa/s take 16 ms, three times the 5 ms deadline. Even 4 samples take 4 ms and leave no margin.
Specification:
- Raise fs to 12 kSa/s. Sixteen samples then take 1.33 ms, comfortably inside 5 ms, and the extra samples give averaging headroom.
- Average an integer number of ripple periods: 10 samples = one 1.2 kHz period, so average 20 samples (1.67 ms) to cancel the ripple rather than smear it.
- Random noise falls by √20 ≈ 4.5, from 1.2 mV to about 0.27 mV, i.e. 0.07 LSB - 5 g becomes resolvable with margin.
- Add a 2nd-order anti-alias filter at 300 Hz in front of the ADC so the 1.2 kHz component is attenuated before it can alias.
- Keep the 12-bit option on hold: after this, quantisation noise (1.155 mV) would become the dominant term, so the upgrade only becomes worthwhile once the averaging and filtering are in place.