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Pancyprian TS Dig. Electronics II study materials
Pancyprian TS Dig. Electronics II study resources

Pancyprian TS Dig. Electronics II: Logic Gates and Combinational Logic Design

Pancyprian TS Dig. Electronics II · Work through your exam, one topic at a time.

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Logic Gates and Combinational Logic Design

Combinational logic questions dominate the paper: you are given a specification in words or a truth table and must produce a minimised expression, then a gate-level implementation. The exam also probes gate characteristics, universality and timing behaviour.

Gate behaviour and universality

  • NAND and NOR are universal: any function can be built from either one alone.
  • XOR outputs 1 when the number of 1 inputs is odd; it is the core of parity, adders and controlled inversion (X = A XOR 1 = A').
  • The standard implementation of an SOP expression is NAND-NAND: each product term becomes one NAND, and a final NAND re-inverts and ORs.
  • Bubbles can be pushed through a gate while swapping AND for OR (De Morgan); this is how active-low signals are handled.
  • Unused TTL inputs must be tied high or low, never floated; unused CMOS inputs must also be tied, because a floating CMOS input can drift and cause oscillation.

Design flow

  1. Write the specification and complete a truth table with every input combination.
  2. Transfer the 1s to a Karnaugh map, group them and read the minimised SOP expression.
  3. Count gate packages, check fan-out and replace with NAND-only if the question requires it.

Worked example

Design a majority voter: output 1 when at least two of A, B, C are 1. The truth table has 1s on rows 011, 101, 110 and 111, so F = A'BC + AB'C + ABC' + ABC. On the K-map the three pairs share the cell 111, giving F = AB + AC + BC. For a NAND-only build, apply double negation: F = ((AB)' · (AC)' · (BC)')', which is three 2-input NANDs feeding one 3-input NAND: four gates in total.

Traps that cost marks

  • Writing a product term with the wrong polarity, for example A B C for row 011 instead of A' B C.
  • Forgetting that the final NAND in a NAND-NAND network performs the OR.
  • Assuming zero propagation delay, then being surprised by a static-1 glitch when two terms change together; the cure is an extra consensus term such as AB in F = A'C + BC.
  • Exceeding fan-out or ignoring capacitive loading on a high-frequency output.
  • Missing rows from the truth table, so the minimised expression is wrong.