Sequential Logic: Flip-Flops, Registers and Counters
Sequential circuits store state, so timing matters as much as logic. The exam tests latch and flip-flop behaviour, the difference between level and edge triggering, counter modulus and decoding, shift-register modes, and the setup/hold rules that keep a design reliable.
Latches and flip-flops
- The SR latch built from NOR gates has an invalid state when both inputs are 1 and a hold state when both are 0; the NAND version swaps the active level.
- A D latch is transparent while the enable is high; a D flip-flop samples D only on the clock edge, which is what makes synchronous design possible.
- JK removes the SR invalid state by toggling when J = K = 1; the T flip-flop is a JK with J and K tied together and divides frequency by 2.
- Setup time is how long data must be stable before the edge; hold time is how long it must remain stable after it. Asynchronous preset and clear act independently of the clock.
Counters and registers
- n flip-flops give a natural modulus of 2^n; a truncated (decade) counter resets or presets early to shorten the sequence.
- Ripple counters are simple but slow: the last stage settles after roughly n propagation delays, and decoded outputs produce short glitches. Synchronous counters clock every stage together and decode cleanly.
- Shift registers move data serially or in parallel (SISO, SIPO, PISO, PIPO); a ring counter has n states, a Johnson (twisted-ring) counter has 2n states.
Worked example
Build a decade counter from a 4-bit binary counter with asynchronous active-low clear. Counts 0 to 9 are wanted, so the clear must be asserted when the next state is 1010. Detecting Q3 = 1 and Q1 = 1 with a NAND gate drives the clear low at count 10, and the counter returns to 0000, giving exactly ten states. The 1010 state exists only for the gate delay, so never decode the final count with a slow gate chain; use it directly into the asynchronous clear.
Traps that cost marks
- Using a level-sensitive latch where the question demands edge-triggered storage.
- Forgetting that clear and preset inputs are usually active-low.
- Decoding the wrong terminal count, producing modulus 9 or 11 instead of 10.
- Ignoring accumulated ripple delay when the counter drives a decoder or a display.
- Confusing ring counters (n states) with Johnson counters (2n states).