Memory Devices and Programmable Logic
This domain covers how data is stored and how a memory map is built, then moves to programmable devices that replace random glue logic. Expect capacity and address-line calculations, chip-select decoding, and questions on the internal structure of PLDs and FPGAs.
Memory organisation
- Capacity = 2^(address lines) x word width. A chip with 13 address lines and 8 data lines holds 8192 words of 8 bits, i.e. 8 KiB or 64 kbit.
- SRAM is fast, built from six-transistor cells, volatile, and needs no refresh. DRAM stores charge on a capacitor, is denser and cheaper per bit, and must be refreshed, which is why it uses row and column addressing.
- ROM family: mask ROM is programmed at manufacture; PROM is one-time field programmable; EPROM is erased by ultraviolet light; EEPROM is electrically erasable per byte; Flash is electrically erasable in blocks.
- Control pins are chip select, output enable and write enable; address decoding maps each chip into a distinct range.
Programmable logic
- PLA has programmable AND and programmable OR arrays; PAL has a programmable AND array with a fixed OR array; GAL adds EEPROM technology and reprogrammability.
- CPLDs use macrocells with wide product-term logic; FPGAs use look-up tables and a routing fabric.
- SRAM-based FPGAs lose configuration at power-off and must be loaded at boot; antifuse and flash devices retain it. JTAG is the usual programming and boundary-scan interface.
Worked example
A 27C256 EPROM is marked 32K x 8. Total capacity is 32768 bytes = 32 KiB = 256 kbit, so it needs 15 address lines (2^15 = 32768) plus 8 data lines. Mapped at the bottom of the map it occupies 0000H to 7FFFH; the next device would start at 8000H. Note that 256 kbit and 32 KiB describe the same device.
Traps that cost marks
- Mixing up kbit and kbyte, a factor-of-eight error.
- Forgetting that DRAM needs refresh, or that SRAM-based FPGAs need configuration at power-up.
- Assuming Flash can erase a single byte rather than a whole sector.
- Off-by-one errors when writing an address range: 8 KiB is 0000H to 1FFFH, not 2000H.
- Forgetting that a chip is inactive unless its chip select is asserted.