Microcontrollers and Microprocessor Fundamentals
This domain moves from discrete logic to programmed devices. The exam tests CPU architecture, bus structure, the instruction cycle, memory and I/O organisation, and the use of timers and interrupts in realistic small programs.
Architecture
- The CPU contains the ALU, the control unit and registers: program counter, instruction register, stack pointer, accumulator and status flags.
- Von Neumann architecture shares one bus for program and data; Harvard architecture uses separate program and data paths, which allows instruction fetch and data access in the same cycle.
- RISC favours simple fixed-length instructions and pipelining; CISC favours powerful multi-cycle instructions.
- Address bus width sets the address space (n lines give 2^n locations); data bus width sets the word size.
- I/O is either memory-mapped, sharing the data address space, or in a separate port space as on the 8051.
Operation and peripherals
- The instruction cycle is fetch, decode, execute, and is built from machine cycles made of clock cycles.
- Standard 8051 cores use 12 clock cycles per machine cycle, so a 12 MHz crystal gives a 1 microsecond machine cycle. PIC cores use 4 clock cycles per instruction cycle, so the instruction rate is Fosc/4.
- Interrupts save context, vector to an ISR, and return; latency and priority matter. Polling is simpler but wastes processor time.
- Timers often include a prescaler; PWM, UART, SPI, I2C and GPIO with direction registers are the usual on-chip peripherals, plus a watchdog timer for recovery.
Worked example
An 8051 runs from a 12 MHz crystal, so one machine cycle is 12/12 MHz = 1 microsecond. Timer 0 in 16-bit mode counts up and overflows at 65536. For a 50 ms delay, 50000 counts are needed, so the reload value is 65536 - 50000 = 15536 = 3CB0H, with TH0 = 3CH and TL0 = B0H, giving 50 ms per overflow.
Traps that cost marks
- Using the crystal frequency directly as the instruction rate.
- Forgetting the prescaler when calculating timer periods.
- Failing to clear the interrupt flag or re-enable interrupts in the ISR.
- Assuming the stack lives in external memory rather than internal RAM.
- Mixing up which registers hold the high and low bytes of a 16-bit reload.