12 V to 3.3 V with a Burst Load: Is a Bigger LDO Enough?
An industrial control board runs from a 12 V rail and needs 3.3 V for a Wi-Fi module plus an MCU. The workload is bursty: 400 mA average, with 700 mA bursts lasting 60 ms every 2 s during association and transmit, plus 40 mA for the MCU. Ambient inside the sealed, unforced-convection enclosure reaches 60 °C. The board is 4-layer with 1 oz copper.
The first prototype uses a fixed 3.3 V LDO in SOT-23-5, θJA = 250 °C/W on this layout, Tj(max) = 125 °C, thermal shutdown at 150 °C, current limit 800 mA. Units reset during transmit bursts. The supply engineer proposes a larger LDO in DPAK (θJA = 45 °C/W) instead of a switching regulator, arguing that "a buck will ruin the ADC noise" (the board also has a 16-bit ADC measuring a 0–10 V sensor input). Bill-of-material cost and board area are constrained but not fixed.
1. Compute the LDO dissipation and junction temperature for both packages at average and burst current, and determine whether either package can work.
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Dissipation.
P = (Vin − Vout) × I = 8.7 V × I
- Average (440 mA): P = 8.7 × 0.44 = 3.83 W
- Burst (740 mA): P = 8.7 × 0.74 = 6.44 W
SOT-23-5 (θJA = 250 °C/W):
Tj = 60 + 3.83 × 250 = 60 + 957 = 1017 °C
Allowed dissipation for Tj ≤ 125 °C: (125 − 60)/250 = 0.26 W → 30 mA of load. The part is not marginal, it is off by more than an order of magnitude.
DPAK (θJA = 45 °C/W):
Tj = 60 + 3.83 × 45 = 60 + 172 = 232 °C - still far above 125 °C.
Allowed dissipation: (125 − 60)/45 = 1.44 W → 1.44/8.7 = 166 mA. Still less than half the 400 mA average, and nowhere near the 740 mA burst.
Conclusion: the linear approach is infeasible in any realistic package at this current and this voltage drop. The resets are thermal shutdown and/or current-limit foldback during bursts - the 800 mA current limit is itself only 60 mA above the burst current, so the two mechanisms overlap. A bigger package is a 3× improvement against a problem that needs 15–30×. Reject the proposal.
2. Design the power architecture, addressing the noise objection quantitatively rather than dismissing it.
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Primary conversion: synchronous buck, 12 V → 3.6 V.
At 440 mA average output (1.58 W), an 88 % efficient buck dissipates:
P = 1.58 × (1/0.88 − 1) = 1.58 × 0.136 = 0.215 W
Even a mediocre 80 % design gives 0.40 W - an order of magnitude below the best LDO number, and compatible with a small SOT-23-6 or 3×3 mm package and no heatsink. Confirm with the vendor's thermal data at 60 °C ambient; the margin is large enough that this is a check, not a design driver.
Secondary: keep a small LDO - as a post-regulator, not as the main converter.
Feed a low-noise LDO from the 3.6 V buck rail to make the analog 3.3 V:
P = (3.6 − 3.3) × I_analog
At 50 mA that is 15 mW - negligible even in SOT-23-5 (Tj rise ≈ 4 °C). This costs almost nothing and gives genuine PSRR at high frequency, where switching spurs actually matter. This directly answers the noise objection: the LDO's benefits are retained where they matter and its dissipation problem is designed out, because the input is no longer 12 V.
Layout and frequency plan for the noise concern:
- Minimise the buck's hot-loop area (input cap → high-side FET → low-side FET → ground return); this, not the regulator choice, dominates radiated and conducted noise.
- Use a shielded inductor and a tight ground pour under the switcher; keep the switching node copper to the minimum that satisfies thermal and EMI.
- Set fsw well away from the ADC's sampling frequency and its harmonics, and away from the vibration/interference bands already present on this machine. Verify with a spectrum sweep rather than assuming.
- Physically separate the analog section and single-point the analog ground to the buck's output capacitor ground.
BOM/area trade: the buck plus inductor plus a few passives is larger and more expensive than a DPAK LDO - but the LDO option does not function. A 60 ms/2 s duty cycle means the burst must be planned for, not averaged away.
3. List the remaining checks that must pass before this architecture is released, including what the burst profile changes.
Read the worked answer
Power path.
- Verify the buck's inductor saturation and output-capacitor ripple current at 740 mA peak, not 400 mA average. The 60 ms burst is long enough that the output capacitor is not a reservoir - the converter itself must deliver 740 mA continuously for 60 ms, and the loop must recover from the load step without dipping below the Wi-Fi module's minimum.
- Check the transient response: a 340 mA step with 60 ms duration stresses the loop's thermal and electrical settling far more than a short spike. Measure the 3.3 V rail with a scope on a 20 MHz-limited bandwidth, triggered on the burst edge, and confirm the deviation stays inside the module's spec - Wi-Fi modules frequently have a 3.0–3.6 V window and briefly draw more than 700 mA during association.
- Re-verify the current-limit margin of whatever feeds this rail, including the 12 V source's own limit and any upstream fuse or connector.
Thermal. 4. Measure, do not only compute: run at 60 °C ambient with a 100 % burst duty cycle (continuous association attempts) for one hour and record the buck's case temperature with a thermocouple. Design for that worst case, not for the 3 % duty cycle of normal operation.
Noise. 5. Measure the ADC's noise floor and effective resolution with the Wi-Fi actively transmitting. Compare ENOB against the quiet case. This is the only measurement that settles the engineer's original objection - if the post-regulator and layout are right, the difference should be within a fraction of an LSB; if not, you have found the real problem.
Reliability. 6. Check startup and inrush with the 60 ms load already present (the module may power up mid-burst), and verify no latch-up or brownout-reset loop. Test at both 10.8 V and 13.2 V input rails, and confirm behaviour when the 12 V rail sags during a motor start on the same line - a very common failure in this class of installation.