NEC Computer Engineering flashcards

33 cards. Read the term and the definition here. The deck at the top of this page is optional.

Two's complement negation

Invert every bit of the number and add one. Used to represent negative integers; an n-bit signed value spans minus two to the n minus one up to two to the n minus one minus one.

Karnaugh map grouping

Cells are grouped in sets of 1, 2, 4, 8, or more that are powers of two and adjacent, including wrap-around edges. Each group eliminates the variables that change within it.

Setup and hold time

Setup time is how long data must be stable before the clock edge; hold time is how long it must remain stable after. Violations cause metastable flip-flop outputs.

Functional completeness of NAND

Any Boolean function can be built from NAND gates alone, because NAND can produce NOT, AND, and OR. The same holds for NOR gates.

CMOS dynamic power

Dynamic power equals capacitance times supply voltage squared times switching frequency. Because voltage is squared, lowering the supply voltage cuts dynamic power sharply.

Multiplexer select lines

A multiplexer with 2^k data inputs requires k select lines. Any function of k variables can be implemented by tying each data input to logic 0 or 1.

CPU performance equation

Execution time equals instruction count times cycles per instruction times clock period. Improving any one factor without worsening the others reduces runtime.

Amdahl's law

Speedup equals one divided by the sum of the serial fraction plus the parallel fraction divided by its speedup factor. The serial portion caps total gain.

Load-use hazard stall

A load followed immediately by a consumer of the loaded register needs one pipeline stall, because load data is only available after the memory stage.

Cache address fields

A cache address splits into tag, index, and block offset. Offset bits equal log base two of block size; index bits equal log base two of set count.

Average memory access time

AMAT equals hit time plus miss rate times miss penalty. Reducing miss rate, hit time, or miss penalty all lower the average access cost.

Write-back versus write-through

Write-through updates memory on every store. Write-back updates memory only when a dirty block is evicted, saving bandwidth but requiring a dirty bit.

Translation lookaside buffer

A small cache of recent virtual-to-physical page translations. A TLB hit avoids a page-table walk; a miss triggers hardware or software page-table lookup.

RISC versus CISC

RISC uses fixed-length instructions and register-to-register operations with simple decoding. CISC uses variable-length, memory-operand instructions often decoded by microcode.

Volatile pointer for registers

Peripheral registers can change outside program control, so they must be accessed through volatile pointers. Otherwise the compiler may cache or reorder accesses.

Watchdog timer

A counter that resets the microcontroller if firmware fails to refresh it in time. It recovers from hangs and must be serviced from normal code paths.

ADC least significant bit

The voltage represented by one converter code equals the reference voltage divided by two to the n, where n is the bit resolution.

UART versus SPI versus I2C

UART is asynchronous with start and stop bits. SPI is synchronous, full-duplex, and uses chip select. I2C uses two wires with addressed devices and acknowledgments.

Interrupt service routine brevity

Handlers should do minimal work, such as setting a flag or moving data, then return. Long handlers increase latency for other interrupts and can drop events.

PWM average output

A pulse-width-modulated pin toggles at a set frequency. The average voltage equals duty cycle times supply voltage, so duty controls delivered power.

Process versus thread

A process has its own address space and resources. Threads within a process share code, data, and heap but keep separate stacks and register state.

Deadlock four conditions

Deadlock requires mutual exclusion, hold-and-wait, no preemption, and circular wait. Removing or preventing any single condition prevents deadlock.

Priority inheritance

When a low-priority task holds a lock needed by a high-priority task, its priority is temporarily raised, limiting the blocking time caused by priority inversion.

Little-endian byte order

The least significant byte of a multi-byte value is stored at the lowest memory address. Big-endian stores the most significant byte first.

Context switch overhead

Switching tasks requires saving and restoring registers and disturbs caches and translation buffers. Very small scheduling quanta waste time on these switches.

TCP versus UDP

TCP establishes a connection and guarantees ordered, reliable delivery with flow control. UDP sends datagrams without retransmission, suiting real-time and telemetry traffic.

Subnet usable host count

With h host bits remaining, usable addresses equal two to the h minus two, because the all-zero network address and all-ones broadcast address are reserved.

Sliding window throughput

Achievable throughput is limited by window size divided by round-trip time. Larger windows or shorter round trips raise the ceiling on unacknowledged data.

ARP and DNS roles

ARP maps an IPv4 address to a hardware MAC address on the local link. DNS maps human-readable host names to IP addresses across the internet.

CAN bus arbitration

Nodes transmit identifiers and the lowest numeric identifier wins contention, because dominant bits override recessive ones. Losing nodes retry without corruption.

RC time constant

The product of resistance and capacitance sets the charging rate. A capacitor reaches about 63 percent of final voltage in one time constant and about 99 percent in five.

Nyquist sampling criterion

The sampling rate must exceed twice the highest frequency present in the signal. Otherwise aliasing folds high frequencies into lower ones, and an anti-alias filter is required.

MTBF and failure rate

Mean time between failures equals one divided by the failure rate. For a constant failure rate, reliability over time t is the exponential of minus lambda times t.