NEC Computer Engineering cheat sheet

Combinational output depends only on present inputs; sequential output depends on present inputs plus stored state (flip-flops, registers, memory).

De Morgan: NOT(A AND B) = (NOT A) OR (NOT B); NOT(A OR B) = (NOT A) AND (NOT B). NAND and NOR are each functionally complete.

Boolean simplification targets minimal literal count: Karnaugh maps group 1, 2, 4, 8 adjacent cells (powers of two), wrapping across edges and corners; don't-care terms may be grouped freely.

Sum-of-products builds an AND term per 1-minterm then ORs them; product-of-sums groups 0-maxterms. Canonical SOP uses every minterm where f = 1.

A D flip-flop samples D at the clock edge; a JK flip-flop toggles when J = K = 1 and holds when J = K = 0. Setup and hold times bound valid data windows around the active edge.

A modulo-N counter needs ceil(log2 N) flip-flops; unused states in a truncated counter must be forced back into the valid sequence.

Two's complement: negate by inverting all bits and adding 1. An n-bit signed range is -2^(n-1) to 2^(n-1) - 1; overflow occurs when two same-sign operands yield the opposite sign.

Static CMOS power splits into dynamic (CV^2 f, from switching) and static leakage; dynamic power falls with supply voltage squared, so voltage scaling dominates energy savings.

A multiplexer with 2^k data inputs needs k select lines; it can implement any k-variable function by tying inputs to 0 or 1.

CPU time = instruction count x CPI x clock period; average CPI = sum(CPI_i x fraction_i) across instruction classes.

Amdahl's law: speedup = 1 / ((1 - p) + p/s), where p is the parallelizable fraction and s the improvement factor; the serial fraction caps speedup.

Classic 5-stage RISC pipeline: IF, ID, EX, MEM, WB. Ideal CPI is 1; stalls from data, control, and structural hazards raise the effective CPI.

Data forwarding bypasses EX/MEM results to later instructions; a load-use hazard still needs one stall because load data arrives after MEM.

Direct-mapped cache address splits into tag | index | offset; offset bits = log2(block size), index bits = log2(number of sets).

AMAT = hit time + miss rate x miss penalty. Set-associative caches reduce conflict misses; larger blocks reduce compulsory misses but raise miss penalty.

Write-through keeps memory current but costs bandwidth; write-back writes only on eviction and needs a dirty bit per block.

Virtual memory maps virtual to physical pages via a page table; the TLB caches recent translations, and a TLB miss triggers a page-table walk.

RISC favors fixed-length instructions and register-register ALU ops; CISC favors variable-length, memory-operand instructions decoded by microcode.

Memory-mapped I/O places peripheral registers in the address space; access them through volatile pointers so the compiler cannot cache or reorder reads.

Polling burns CPU cycles; interrupts free the CPU but add latency from context save, vector fetch, and handler entry.

An ISR should be short: set a flag or push data, then defer heavy work to the main loop or a lower-priority task.

NVIC-style priority: a higher-priority interrupt preempts a lower one; priority grouping splits bits between preemption and subpriority.

A watchdog timer resets the MCU unless firmware periodically refreshes it; it recovers from hangs but must be serviced in the main loop, not only in one ISR.

UART is asynchronous and needs matched baud rates plus start/stop bits; SPI is synchronous, full-duplex, uses chip-select lines; I2C is a two-wire bus with 7-bit addresses and ACK bits.

ADC resolution: LSB size = Vref / 2^n. An ideal n-bit converter over a full-scale range Vref resolves Vref/2^n per code.

PWM duty cycle D gives average output D x Vsupply; frequency sets period, and duty sets on-time.

Cross-compilation builds target code on a host; startup code sets the stack pointer and copies initialized data from flash to RAM before main().

A process owns an address space; threads share code, data, and heap but keep private stacks and registers.

Context switch cost = save/restore registers plus TLB and cache disturbance; it is pure overhead relative to useful work.

Round-robin quantum too small raises switch overhead; too large degrades to first-come-first-served.

Priority inversion: a low-priority holder blocks a high-priority waiter; priority inheritance raises the holder's priority to bound the delay.

A mutex provides mutual exclusion and ownership; a semaphore is a counter without ownership and can signal between tasks.

Deadlock needs all four: mutual exclusion, hold-and-wait, no preemption, circular wait. Break any one to prevent it.

Virtual address translation: page number indexes the page table, offset is copied unchanged; page size determines offset width.

Little-endian stores the least significant byte at the lowest address; big-endian stores the most significant byte first.

Big-O: binary search O(log n), balanced-tree lookup O(log n), hash lookup O(1) average, comparison sort O(n log n) lower bound.

TCP is connection-oriented, reliable, ordered, and flow-controlled; UDP is connectionless with no retransmission, suited to streaming and telemetry.

TCP handshake is SYN, SYN-ACK, ACK; teardown uses FIN/ACK in both directions.

Sliding window throughput is bounded by window size / round-trip time; a bigger window or shorter RTT raises throughput.

IPv4 header is 20 bytes minimum; the TTL field decrements per hop and reaching zero drops the packet.

Subnetting: host bits = 32 - prefix length; usable hosts = 2^hostbits - 2 (network and broadcast reserved).

ARP resolves IPv4 to MAC on a local link; DNS resolves names to addresses; DHCP assigns addresses dynamically.

CRC detects burst errors using polynomial division; parity detects only odd numbers of bit errors.

OSI layers: physical, data link, network, transport, session, presentation, application. Switches act at layer 2, routers at layer 3.

CAN bus is a multi-master differential bus with arbitration by identifier; lower numeric IDs win contention, and dominant bits override recessive.

Ohm's law V = IR; power P = VI = I^2 R = V^2 / R. Resistors in series add; in parallel the reciprocal sums.

RC time constant tau = RC; a capacitor charges to about 63% of final value in one tau and about 99% in five tau.

Nyquist: sample above twice the highest signal frequency to avoid aliasing; an anti-alias filter must precede the sampler.

An ideal op-amp has infinite gain and input impedance and zero output impedance; in a negative-feedback configuration the closed-loop gain is set by external components.

A diode conducts above its forward drop (about 0.7 V for silicon); a BJT needs Vbe near 0.7 V to turn on.

Decoupling capacitors near IC power pins shunt high-frequency supply noise to ground and supply transient current.

Synchronous design uses a single clock; clock skew and setup/hold violations cause metastability, and synchronizers are needed for asynchronous inputs.

PCB transmission lines need impedance matching to prevent reflections; series termination at the driver damps ringing.

Signal-to-noise ratio in dB = 20 log10(signal/noise) for voltage; 6 dB corresponds to a factor of two.

Fault models: stuck-at-0/1, bridging, open, and delay faults. Test coverage measures the fraction of modeled faults detected.

A test detects a fault only if it produces a difference between good and faulty output; untestable nodes need design-for-test access.

Boundary scan (JTAG) shifts test data through a chain of boundary cells to test board interconnects without physical probes.

Built-in self-test generates patterns and checks responses on-chip, trading area for test time and field diagnostics.

MTBF = 1 / failure rate; reliability R(t) = exp(-lambda t) for a constant failure rate.

Redundancy (duplication, voting, error-correcting codes) raises reliability; a spare must be detected and switched in to help.

EMC: shielding, twisted pairs, and ground planes reduce emissions and susceptibility; a single-point ground avoids ground loops.

Safety and liability: engineering decisions are documented, and a known hazard must be corrected or disclosed rather than ignored.

Version control, code review, and reproducible builds are standard practice; a released binary must be traceable to its source revision.