NEC Computer Engineering study plan
NEC Computer Engineering · Give each week a clear focus.
8 weeks · About 6 hours per week
Computer Engineering (official domain breakdown not published in source)
Map the exam blueprint against your own background and rank topics by personal weakness rather than by textbook order.
Build a one-page formula and unit-conversion sheet covering electrical quantities, number systems, and power/energy relations, then verify every entry against a first-principles derivation.
Solve 20 basic circuit problems (series/parallel resistance, voltage and current dividers, Thevenin equivalents) without notes and log every error with its root cause.
Set up a spaced-repetition deck for constants, definitions, and standard symbols, capped at 15 new cards per day.
Your checkpoint
A weakness-ranked topic matrix plus an error log covering at least 20 solved circuit problems.
Computer Engineering (official domain breakdown not published in source)
Analyze RLC circuits in both transient and steady-state regimes, deriving time constants and resonant frequency from component values rather than memorizing formulas.
Compute AC power quantities including real, reactive, and apparent power, and explain power factor correction numerically for two worked loads.
Model a diode and a bipolar transistor in each operating region and calculate bias points for at least three amplifier configurations.
Explain operational-amplifier behavior for inverting, non-inverting, and integrator topologies, including slew-rate and bandwidth limits.
Your checkpoint
A worked solutions packet of 12 analog problems (RLC, power, transistor bias, op-amp) with derivations shown step by step.
Computer Engineering (official domain breakdown not published in source)
Convert between binary, octal, hexadecimal, and two's-complement representations by hand for 8-, 16-, and 32-bit widths, including overflow cases.
Simplify Boolean expressions using algebraic manipulation and Karnaugh maps, then confirm each result with a truth table.
Design and trace combinational blocks: adders, multiplexers, decoders, and comparators, and state propagation-delay paths.
Compare latch and flip-flop timing behavior and identify setup and hold violations in a given timing diagram.
Your checkpoint
A design notebook containing five combinational circuits with truth tables, minimized expressions, and gate-level schematics.
Computer Engineering (official domain breakdown not published in source)
Trace synchronous sequential machines from state diagram to state table to excitation equations for D and JK flip-flops.
Design a counter or finite-state machine with a specified modulus and verify the sequence by hand simulation.
Estimate critical-path delay for a small datapath by summing gate and interconnect delays.
Complete a timed 40-question mixed drill on number systems, Boolean algebra, and sequential logic under exam conditions.
Your checkpoint
A closed-book mock section scored at 70 percent or better, with a written review of every missed item.
Milestones
Week 4: Score at least 70 percent on a timed 40-question closed-book drill spanning circuits, analog electronics, and digital logic, and show a corrected error log for every miss.