NEC Computer Engineering key terms

The relationship stating that voltage across a conductor equals current through it multiplied by its resistance, written V = I × R. It underpins nearly all DC circuit analysis and resistor selection.

The principle that the algebraic sum of all voltages around any closed loop in a circuit equals zero. It lets you write loop equations to solve for unknown currents and node voltages.

The principle that the total current entering a node equals the total current leaving it, since charge cannot accumulate at an ideal junction. It forms the basis of nodal analysis.

A technique replacing any linear two-terminal network with a single voltage source in series with one resistance. It simplifies load calculations and maximum power transfer analysis.

A method for linear circuits where the response from multiple independent sources equals the sum of responses computed with each source acting alone, other sources deactivated appropriately.

A configuration of two or more resistors in series where output voltage is a fraction of input voltage proportional to resistance ratios. Commonly used for biasing and reference generation.

The maximum wattage a resistor can dissipate safely without overheating, computed as I²R or V²/R. Choosing an undersized rating causes drift or failure in real circuits.

The product of resistance and capacitance, denoted tau, giving the time for a capacitor to charge to about 63 percent of its final voltage. It sets transient response speed in filters and timing circuits.

A circuit that passes frequencies below a cutoff while attenuating higher ones, often built from a resistor and capacitor. Cutoff frequency equals one over two pi RC.

A graph of a circuit's magnitude and phase response versus frequency on logarithmic axes. Engineers use it to read gain, cutoff frequency, and stability margins quickly.

A high-gain differential voltage amplifier used with external feedback to build amplifiers, filters, and comparators. Ideal models assume infinite gain, infinite input impedance, and zero output impedance.

Returning a fraction of an amplifier's output to its inverting input to reduce gain but improve stability, bandwidth, and linearity. It is the core principle behind most analog control loops.

A circuit comparing two input voltages and outputting a binary high or low state. Unlike op-amps used linearly, comparators are intended to operate open-loop or with hysteresis.

The voltage drop across a conducting diode, roughly 0.7 V for silicon and 0.3 V for Schottky types. It must be accounted for in power and level-shifting calculations.

A diode designed to operate in reverse breakdown at a specified voltage, providing a stable reference. It is commonly used for simple voltage regulation and overvoltage clamping.

Four diodes arranged so that both half-cycles of an AC input produce a unipolar output. It is the first stage of most linear power supplies.

A circuit that maintains a constant output voltage by dissipating excess power as heat across a pass transistor. It offers low noise but poor efficiency at large input-output differences.

A switching regulator that steps voltage down using an inductor, switch, and diode or synchronous rectifier. It achieves high efficiency by chopping and averaging energy rather than dissipating it.

A technique controlling average power by varying the duty cycle of a fixed-frequency square wave. It is used in motor drives, LED dimming, and switching power supplies.

The fraction of a period during which a periodic signal is high, usually expressed as a percentage. It directly determines average voltage or power delivered by a switching circuit.

A mathematical system of logic using variables with values true or false and operators AND, OR, and NOT. It enables simplification of digital logic expressions before implementation.

Two identities showing that the negation of a conjunction equals the disjunction of negations, and vice versa. They allow conversion between AND and OR forms using NAND or NOR gates.

A grid layout of truth-table outputs arranged by Gray code so adjacent cells differ by one variable. Grouping ones yields a minimal sum-of-products expression.

A combinational circuit that selects one of several data inputs and routes it to a single output under control of select lines. It is widely used for data routing and function implementation.

A combinational circuit that activates one of many outputs based on a binary input code. It is used for memory addressing and selecting peripheral devices.

A tabulation listing every combination of input values for a logic function alongside the corresponding output. It is the starting point for designing and verifying combinational circuits.

A bistable storage element holding one bit until clocked or otherwise triggered. Types include D, JK, and T, each with distinct excitation behavior.

The intervals before and after a clock edge during which a flip-flop's data input must remain stable. Violating them causes metastability and unreliable capture.

The difference in arrival time of a clock edge at different sequential elements. Excessive skew can cause hold violations or reduce the maximum operating frequency.

A model of sequential behavior with a finite set of states, transitions triggered by inputs, and outputs. Moore outputs depend only on state; Mealy outputs also depend on inputs.

A group of flip-flops storing a multi-bit word, often with a shared clock and optional load enable. Registers form the storage backbone of datapaths and pipelines.

The longest delay path between two sequential elements in a synchronous design. It sets the minimum clock period and therefore the maximum clock frequency.

The property ensuring all processors observe a consistent view of shared memory despite private caches. Protocols such as MESI track sharing and ownership states per cache line.

A layered arrangement of small fast memories close to the processor backed by larger slower levels. Locality of reference makes multi-level caching effective.

An abstraction giving each process a private address space mapped to physical frames by the memory management unit. It enables protection, sharing, and demand paging.

A small associative cache holding recent virtual-to-physical address translations. A miss requires a page-table walk, adding latency to memory access.

An addressing scheme where device registers appear at ordinary memory addresses, accessed with normal load and store instructions. It simplifies programming but consumes address space.

A controller transferring data between peripherals and memory without per-byte CPU involvement. It frees the processor but requires coherent buffer management.

An asynchronous signal causing the processor to suspend current execution and run a handler. Interrupts provide responsive I/O without polling.