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NEC Computer Engineering practice questions

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Question 1Computer Engineering (official domain breakdown not published in source)

In a synchronous sequential circuit, which quantity limits the maximum clock frequency when only combinational logic delay and flip-flop timing parameters are considered?

  1. The sum of the flip-flop clock-to-Q delay, the longest combinational path delay, and the setup time Correct answer.
  2. The flip-flop hold time alone
  3. The clock-to-Q delay divided by the number of pipeline stages
  4. The average of all combinational path delays

Explanation

The setup-time constraint requires data to arrive at the destination flip-flop before the next active clock edge. The worst-case path therefore includes the source clock-to-Q delay, the longest combinational propagation delay, and the destination setup time, all within one clock period.

Question 2Computer Engineering (official domain breakdown not published in source)

A two-input CMOS NAND gate has both inputs at logic 1. Which transistors are conducting in a standard static CMOS implementation?

  1. Both NMOS pull-down transistors and both PMOS pull-up transistors
  2. Only the PMOS pull-up transistors, with the NMOS network off
  3. One NMOS pull-down transistor and one PMOS pull-up transistor
  4. Both NMOS pull-down transistors, with the PMOS pull-up network off Correct answer.

Explanation

In a static CMOS NAND gate the NMOS devices are in series to ground and the PMOS devices are in parallel to the supply. With both inputs high, both series NMOS devices conduct and pull the output low, while both parallel PMOS devices are off.

Question 3Computer Engineering (official domain breakdown not published in source)

Which statement correctly describes the role of the Translation Lookaside Buffer in a virtual-memory system?

  1. It stores recently used virtual-to-physical page mappings to avoid a page-table walk on every access Correct answer.
  2. It enforces the page-replacement policy by tracking reference and dirty bits
  3. It holds the contents of the most recently accessed cache lines during a context switch
  4. It converts physical addresses into virtual addresses before the MMU issues a memory request

Explanation

The TLB is a small associative cache of page-table entries. A hit supplies the physical frame number directly, avoiding the multi-level page-table walk; a miss triggers the walk and then fills the TLB.

Question 4Computer Engineering (official domain breakdown not published in source)

In the IEEE 754 single-precision format, what is represented when the exponent field is all zeros and the fraction field is nonzero?

  1. A normal number with an implied leading one
  2. A quiet NaN
  3. Positive or negative infinity
  4. A subnormal number with an implied leading zero and exponent 1 minus the bias Correct answer.

Explanation

An all-zero exponent with a nonzero fraction encodes a subnormal value. The significand has an implied leading 0 rather than 1, and the effective exponent is fixed at 1 minus the bias, which extends the representable range near zero with reduced precision.

Question 5Computer Engineering (official domain breakdown not published in source)

A pipelined processor executes an instruction stream with no hazards. If the pipeline has 5 stages and each stage takes one cycle, how many cycles are needed to complete 20 instructions in steady state?

  1. 100
  2. 24 Correct answer.
  3. 20
  4. 25

Explanation

The first instruction fills all five stages, taking 5 cycles, and each subsequent instruction completes one per cycle. Total cycles equal the number of stages plus the number of instructions minus one, giving 5 + 20 - 1 = 24.

Question 6Computer Engineering (official domain breakdown not published in source)

Which hazard is created when a load instruction is immediately followed by an instruction that uses the loaded register?

  1. A control hazard resolved by branch prediction
  2. A write-after-write hazard on the program counter
  3. A structural hazard on the instruction cache port
  4. A data hazard requiring a stall or forwarding from the memory stage Correct answer.

Explanation

A load produces its result only at the end of the memory stage, later than an ALU result. A dependent instruction therefore needs either a stall or a forwarding path from the memory-stage output to the execute stage.

Question 7Computer Engineering (official domain breakdown not published in source)

In a RISC-V pipeline, what is the purpose of the branch target buffer?

  1. To hold the branch history register used only for two-bit saturating counters
  2. To cache the predicted target address of a branch so it can be fetched before the branch resolves Correct answer.
  3. To store the return address of every function call in a dedicated stack
  4. To record the resolved outcome of every load instruction

Explanation

A branch target buffer keeps previously seen branch addresses paired with their targets. On a predicted-taken branch, the fetch stage can redirect to the cached target immediately instead of waiting for decode or execute to compute it.

Question 8Computer Engineering (official domain breakdown not published in source)

Which statement best characterizes the difference between a von Neumann and a Harvard architecture?

  1. Von Neumann machines cannot execute stored programs, whereas Harvard machines can
  2. Von Neumann machines require direct memory access, while Harvard machines forbid it
  3. Harvard machines lack a program counter, while von Neumann machines require one
  4. Harvard machines use separate instruction and data memories, while von Neumann machines share one address space Correct answer.

Explanation

The Harvard model provides distinct instruction and data paths, allowing simultaneous fetch of an instruction and a data operand. The von Neumann model uses a single memory and bus for both, which can create structural conflicts.

Question 9Computer Engineering (official domain breakdown not published in source)

A byte-addressable system uses 32-bit addresses and a direct-mapped cache with 16-byte blocks and 256 sets. Which address bits form the block offset and the set index?

  1. Offset bits 5:0, index bits 13:6
  2. Offset bits 4:0, index bits 12:5
  3. Offset bits 4:0, index bits 8:5
  4. Offset bits 3:0, index bits 11:4 Correct answer.

Explanation

A 16-byte block needs 4 offset bits to address each byte within the block. With 256 sets, the index needs 8 bits, and those bits sit immediately above the offset, occupying positions 11 through 4.

Question 10Computer Engineering (official domain breakdown not published in source)

Which protocol behavior is characteristic of a snooping-based cache coherence scheme on a shared bus?

  1. Caches exchange coherence messages exclusively through a dedicated point-to-point ring
  2. A central directory tracks sharers and forwards requests only to the recorded nodes
  3. Each cache monitors bus transactions and invalidates or updates its copy when another core writes a shared line Correct answer.
  4. Coherence is maintained by flushing the entire cache on every write by any core

Explanation

In snooping, all caches observe the shared bus. When a write appears, each cache checks whether it holds the affected line and responds by invalidating or updating its copy according to the protocol state.

Question 11Computer Engineering (official domain breakdown not published in source)

In a 5-stage RISC pipeline with full forwarding, a dependent ALU instruction immediately after an ALU instruction requires how many stall cycles?

  1. One, because the result is unavailable until the writeback stage
  2. Three, because the pipeline must drain before forwarding
  3. Zero, because the ALU result can be forwarded to the next instruction's execute stage Correct answer.
  4. Two, because the register file cannot be read and written in the same cycle

Explanation

With full forwarding, the result produced at the end of the execute stage is routed directly to the execute stage of the following instruction. No stall is needed for an ALU-to-ALU dependency, although a load-use pair still requires one.

Question 12Computer Engineering (official domain breakdown not published in source)

Which statement about DRAM refresh is accurate?

  1. Refresh is performed only when the CPU executes a cache flush instruction
  2. Refresh improves bandwidth by allowing multiple rows to be activated simultaneously
  3. Each row must be periodically refreshed because the storage capacitor leaks charge Correct answer.
  4. Refresh is unnecessary in DRAM because each cell is a pair of cross-coupled inverters

Explanation

A DRAM cell stores a bit as charge on a capacitor accessed through a transistor. Leakage gradually destroys that charge, so the controller must periodically sense and rewrite each row within the retention interval.

Question 13Computer Engineering (official domain breakdown not published in source)

A system uses 4-way set-associative replacement with LRU policy. Within one set, the ways are accessed in the order 0, 1, 2, 3, 0, 1, 2. Which way is selected for replacement on the next miss?

  1. Way 3 Correct answer.
  2. Way 1
  3. Way 2
  4. Way 0

Explanation

After the access sequence, way 3 is the least recently used because it has not been touched since the initial fill while ways 0, 1, and 2 were all re-accessed. LRU therefore evicts way 3 on the next miss.

Question 14Computer Engineering (official domain breakdown not published in source)

Which condition must hold for a set of processes to be in a safe state in the Banker's algorithm?

  1. Every process currently holds at least one resource instance
  2. The total number of resource instances exceeds the sum of all maximum claims
  3. No process has ever been blocked waiting for a resource
  4. There exists an ordering in which each process's remaining maximum claim can be satisfied by the currently available resources plus those held by earlier processes Correct answer.

Explanation

A safe state guarantees that some sequence exists in which each process can finish using available resources plus resources released by predecessors. If no such sequence exists, the state is unsafe and deadlock may become possible.

Question 15Computer Engineering (official domain breakdown not published in source)

What is the primary function of the memory management unit in a processor?

  1. To compress cache lines before writing them to main memory
  2. To arbitrate interrupts from external devices
  3. To schedule threads onto available cores
  4. To translate virtual addresses to physical addresses and enforce access permissions Correct answer.

Explanation

The MMU performs address translation using page tables and checks permission bits on each access. It raises a fault when a translation is missing or an access violates the protection settings.

Question 16Computer Engineering (official domain breakdown not published in source)

Which property distinguishes a hardwired control unit from a microprogrammed control unit?

  1. Hardwired control generates signals with dedicated combinational logic, while microprogrammed control sequences microinstructions from a control store Correct answer.
  2. Hardwired control requires a microsequencer, while microprogrammed control requires only a ring counter
  3. Hardwired control stores control signals in a writable control store, while microprogrammed control uses fixed logic gates
  4. Hardwired control executes one instruction per microinstruction, while microprogrammed control executes one instruction per clock edge

Explanation

Hardwired control implements the control function directly in combinational logic and state machines, which is fast but inflexible. Microprogrammed control fetches microinstructions from a control store, making the design easier to modify at the cost of additional sequencing overhead.

Question 17Computer Engineering (official domain breakdown not published in source)

Which statement about a direct memory access controller is correct?

  1. It can transfer data only when the CPU is halted
  2. It replaces the interrupt controller by handling all device interrupts
  3. It transfers data between a device and memory without the CPU executing a load or store for each item Correct answer.
  4. It requires the CPU to poll a status register after every transferred byte

Explanation

A DMA controller performs block transfers directly between a peripheral and memory, freeing the CPU from per-item load and store instructions. The CPU programs the transfer and is notified on completion, often by interrupt.

Question 18Computer Engineering (official domain breakdown not published in source)

In a two-level page table with 4 KiB pages and 32-bit virtual addresses, each level indexing 1024 entries, how many bits are used for each level's index?

  1. 10 Correct answer.
  2. 8
  3. 12
  4. 14

Explanation

With 1024 entries per table, each level index requires 10 bits because 2^10 equals 1024. The remaining 12 bits address the offset within a 4 KiB page, and two 10-bit indices cover 20 bits of page number.

Question 19Computer Engineering (official domain breakdown not published in source)

What is the effect of increasing the associativity of a cache while holding total capacity and block size constant?

  1. The block size increases, which reduces compulsory misses
  2. The tag width decreases, which increases the number of index bits
  3. The number of sets decreases, which can reduce conflict misses but may increase access latency Correct answer.
  4. The number of sets increases, which always reduces capacity misses

Explanation

With fixed capacity and block size, more ways per set means fewer sets. Fewer sets reduce the chance that distinct blocks collide in the same set, but the additional comparators and multiplexing can lengthen the hit path.

Question 20Computer Engineering (official domain breakdown not published in source)

Which statement correctly describes the role of the program counter during instruction execution?

  1. It holds the base address of the page table for the current process
  2. It holds the address of the next instruction to be fetched and is updated by sequential increment or by a taken branch Correct answer.
  3. It stores the operand currently being read by the ALU
  4. It records the number of instructions retired since reset

Explanation

The program counter supplies the fetch address for the next instruction. It normally advances by the instruction length, but a taken branch or jump loads it with the target address.

Question 21Computer Engineering (official domain breakdown not published in source)

A system has a 95% instruction cache hit rate and a 90% data cache hit rate. If instruction fetches constitute 60% of all memory references, what is the overall hit rate across both caches?

  1. 0.93 Correct answer.
  2. 0.90
  3. 0.92
  4. 0.95

Explanation

The overall rate is the weighted average of the two hit rates by reference share. Computing 0.6 times 0.95 plus 0.4 times 0.90 gives 0.57 plus 0.36, which equals 0.93.

Question 22Computer Engineering (official domain breakdown not published in source)

Which technique allows a superscalar processor to execute multiple independent instructions in the same cycle?

  1. Increasing the clock frequency while keeping the datapath unchanged
  2. Deepening the pipeline by splitting each stage into two
  3. Using a single-issue in-order pipeline with a larger instruction cache
  4. Issuing several instructions per cycle to distinct functional units after checking dependencies Correct answer.

Explanation

Superscalar execution relies on fetching and dispatching more than one instruction per cycle to parallel functional units. Dependency checking ensures that only independent instructions proceed together.

Question 23Computer Engineering (official domain breakdown not published in source)

What is the primary purpose of the exclusive cache state in a MESI-style coherence protocol?

  1. To allow a single core to modify a line without broadcasting an invalidation on every write Correct answer.
  2. To force every read to consult main memory before returning data
  3. To indicate that a line has been evicted from all caches
  4. To permit multiple cores to hold a dirty copy simultaneously

Explanation

The exclusive state records that only one cache holds the line and that it matches memory. A subsequent write can then move to modified without sending an invalidation, reducing coherence traffic for lines that are written by a single core.

Question 24Computer Engineering (official domain breakdown not published in source)

In a RAID 5 array with four disks, what happens to read and write performance relative to a single disk?

  1. Reads can be served in parallel across disks, while each write requires reading old data and parity to compute the new parity Correct answer.
  2. Writes are faster than reads because parity eliminates the need to update data blocks
  3. Both reads and writes scale linearly with the number of disks because parity is stored on a dedicated disk
  4. Reads require all four disks to be accessed simultaneously for every request

Explanation

RAID 5 distributes parity across all disks, so independent reads can proceed in parallel. A small write, however, typically requires reading the old data and old parity to compute the new parity, adding overhead compared with a single disk.

Question 25Computer Engineering (official domain breakdown not published in source)

Which numbering system is used internally by a digital computer to represent data and perform arithmetic?

  1. Hexadecimal
  2. Binary Correct answer.
  3. Decimal
  4. Roman

Explanation

Digital logic circuits have two stable voltage levels, so data is stored and processed in base-2 (binary) form. Hexadecimal and decimal are convenient human notations layered on top of that underlying binary representation.

Question 26Computer Engineering (official domain breakdown not published in source)

In Boolean algebra, which gate produces a HIGH output only when all of its inputs are HIGH?

  1. XOR
  2. OR
  3. NOR
  4. AND Correct answer.

Explanation

The AND function yields 1 only for the input combination where every input is 1. Any single 0 input forces the output to 0.

Question 27Computer Engineering (official domain breakdown not published in source)

What is the function of a multiplexer in a digital system?

  1. It converts a serial bit stream into a parallel word
  2. It selects one of several data inputs and routes it to a single output Correct answer.
  3. It amplifies a weak signal to full logic level
  4. It stores one bit of state until the next clock edge

Explanation

A multiplexer acts as a digitally controlled selector, forwarding one chosen input line to the output based on select signals. This makes it a core building block for data routing and bus sharing.

Question 28Computer Engineering (official domain breakdown not published in source)

Which memory type loses its stored contents when power is removed?

  1. Flash memory
  2. ROM
  3. EEPROM
  4. SRAM Correct answer.

Explanation

SRAM is volatile: it relies on continuous power to hold each bit in a bistable latch. Flash, EEPROM, and ROM are non-volatile technologies that retain data without power.

Question 29Computer Engineering (official domain breakdown not published in source)

In an instruction set architecture, what does an addressing mode specify?

  1. How interrupts are prioritized in the controller
  2. How many pipeline stages the processor contains
  3. How the effective address of an operand is computed Correct answer.
  4. How cache lines are replaced on a miss

Explanation

An addressing mode defines the rule by which an instruction derives the location of its operand, for example immediate, register, or base-plus-offset. This determines how the operand field is interpreted during execution.

Question 30Computer Engineering (official domain breakdown not published in source)

Which statement describes the role of an assembler?

  1. It executes each source statement as it is read
  2. It loads the operating system kernel at boot time
  3. It links separately compiled object files into one executable
  4. It translates mnemonic assembly source into machine code Correct answer.

Explanation

An assembler converts symbolic assembly instructions and labels into the binary machine instructions the processor executes. It performs the translation step but not the linking or loading steps.

Question 31Computer Engineering (official domain breakdown not published in source)

What is the main purpose of an interrupt in a computer system?

  1. To permanently halt all execution until reset
  2. To expand the physical address space
  3. To increase the clock frequency of the CPU
  4. To signal the processor that an event needs attention Correct answer.

Explanation

An interrupt asynchronously notifies the processor that a device or software event requires servicing, causing a transfer of control to a handler. This lets the CPU respond to I/O without continuously polling.

Question 32Computer Engineering (official domain breakdown not published in source)

Which quantity does the clock period of a synchronous digital circuit directly determine?

  1. The number of registers in the design
  2. The width of the data bus
  3. The minimum time allowed for combinational logic between registers Correct answer.
  4. The size of the instruction cache

Explanation

The clock period must be long enough for signals to propagate through the combinational logic and meet setup requirements at the next register. It therefore bounds the worst-case path delay.

Question 33Computer Engineering (official domain breakdown not published in source)

A 10-bit binary number is interpreted as an unsigned integer. What is the largest value it can represent?

  1. 1024
  2. 511
  3. 1023 Correct answer.
  4. 2047

Explanation

An unsigned n-bit number spans 0 through 2^n - 1, so 10 bits give a maximum of 2^10 - 1 = 1023. The value 1024 requires 11 bits.

Question 34Computer Engineering (official domain breakdown not published in source)

A combinational circuit has four inputs. How many rows does its complete truth table contain?

  1. 16 Correct answer.
  2. 8
  3. 32
  4. 4

Explanation

A truth table must list every input combination, giving 2^n rows for n inputs. With four inputs that is 2^4 = 16 rows.

Question 35Computer Engineering (official domain breakdown not published in source)

A byte-addressable memory has a 16-bit address bus. What is its total addressable capacity?

  1. 32 KiB
  2. 16 KiB
  3. 64 KiB Correct answer.
  4. 128 KiB

Explanation

A 16-bit address selects 2^16 = 65536 distinct byte locations, which equals 64 KiB. Each address identifies one byte in a byte-addressable space.

Question 36Computer Engineering (official domain breakdown not published in source)

A two-input XOR gate receives inputs A = 1 and B = 1. What is the output?

  1. Depends on the previous state
  2. Undefined
  3. 0 Correct answer.
  4. 1

Explanation

XOR outputs 1 only when its inputs differ; identical inputs produce 0. Since both inputs are 1, the output is 0.

Question 37Computer Engineering (official domain breakdown not published in source)

Which design change reduces the critical path delay of a long combinational logic block feeding a register?

  1. Inserting pipeline registers to split the logic into stages Correct answer.
  2. Widening the data bus
  3. Increasing the number of cache ways
  4. Adding more general-purpose registers

Explanation

Splitting a long combinational path with intermediate registers shortens the logic between successive registers, allowing a shorter clock period. This is the basis of pipelining for throughput.

Question 38Computer Engineering (official domain breakdown not published in source)

What distinguishes an SRAM cell from a DRAM cell in terms of storage mechanism?

  1. SRAM uses a bistable latch; DRAM stores charge on a capacitor Correct answer.
  2. SRAM is non-volatile; DRAM is volatile
  3. SRAM stores charge on a capacitor; DRAM uses a latch
  4. Both store data as magnetic domains

Explanation

An SRAM bit is held by a cross-coupled latch that keeps its state as long as power is applied. A DRAM bit is a capacitor charge that leaks away and must be refreshed.

Question 39Computer Engineering (official domain breakdown not published in source)

A CPU executes 2 x 10^9 instructions in 1 second. What is its throughput in MIPS?

  1. 2000 Correct answer.
  2. 1000
  3. 4000
  4. 500

Explanation

MIPS counts millions of instructions per second, so 2 x 10^9 instructions per second equals 2000 million per second. Dividing by 10^6 gives the MIPS figure.

Question 40Computer Engineering (official domain breakdown not published in source)

Which statement correctly describes little-endian byte ordering?

  1. Bytes within a word are stored in reverse bit order
  2. The least significant byte of a word is stored at the lowest address Correct answer.
  3. The most significant byte of a word is stored at the lowest address
  4. Only 16-bit values can be stored in little-endian form

Explanation

In little-endian layout the least significant byte occupies the lowest memory address, with higher bytes at increasing addresses. Big-endian reverses this convention.

Question 41Computer Engineering (official domain breakdown not published in source)

An 8-bit register holds the two's complement value 11110110. What decimal value does it represent?

  1. 10
  2. 246
  3. -9
  4. -10 Correct answer.

Explanation

The leading bit is 1, so the value is negative; inverting the bits and adding one gives 00001010, which is 10, so the value is -10. Equivalently, the value equals -128 + 118 = -10.

Question 42Computer Engineering (official domain breakdown not published in source)

Which feature of an instruction set architecture most directly enables position-independent code?

  1. Separate instruction and data caches
  2. A dedicated floating-point unit
  3. PC-relative addressing for branches and data references Correct answer.
  4. A fixed instruction length

Explanation

PC-relative addressing computes targets from the current program counter rather than an absolute address, so the code can be relocated without patching. This supports shared libraries and address-space layout randomization.

Question 43Computer Engineering (official domain breakdown not published in source)

A system uses memory-mapped I/O. How does the processor communicate with a device register?

  1. By executing ordinary load and store instructions to a reserved address Correct answer.
  2. By raising a non-maskable interrupt to the device
  3. By issuing a DMA request for every byte transferred
  4. By using only dedicated IN and OUT instructions

Explanation

In memory-mapped I/O, device registers occupy addresses in the normal address space, so standard load and store instructions access them. This lets the full instruction set and addressing modes apply to I/O.

Question 44Computer Engineering (official domain breakdown not published in source)

A 16-bit data bus transfers one word per bus cycle. How many cycles are needed to move a 64-bit value?

  1. 1
  2. 2
  3. 4 Correct answer.
  4. 8

Explanation

Each cycle carries 16 bits, so a 64-bit value requires 64 / 16 = 4 cycles. The transfer count scales with the ratio of value width to bus width.

Question 45Computer Engineering (official domain breakdown not published in source)

Why does adding more pipeline stages eventually stop improving processor throughput?

  1. The program counter becomes too wide to store
  2. Register overhead and pipeline latency grow while clock skew and hazard costs rise Correct answer.
  3. The instruction set no longer fits in memory
  4. Arithmetic operations become mathematically impossible

Explanation

Each added stage introduces register setup and hold overhead that consumes part of the shortened cycle, and deeper pipelines raise branch-misprediction and dependency penalties. Beyond some depth these costs outweigh the gain in clock rate.

Question 46Computer Engineering (official domain breakdown not published in source)

A cache has a 2% miss rate and a miss penalty of 100 cycles, with a 1-cycle hit time. What is the approximate average memory access time?

  1. 2 cycles
  2. 1.02 cycles
  3. 3 cycles Correct answer.
  4. 100 cycles

Explanation

AMAT equals hit time plus miss rate times miss penalty, so 1 + 0.02 x 100 = 3 cycles. The miss penalty dominates even at a low miss rate.

Question 47Computer Engineering (official domain breakdown not published in source)

A processor uses a 4-bit branch history register indexing a 2-bit saturating counter predictor. What does this scheme primarily exploit?

  1. Correlation between the outcomes of recent branches and the current branch Correct answer.
  2. The absolute address of the branch instruction
  3. The cache line size of the instruction fetch unit
  4. The number of registers available at runtime

Explanation

A branch history register captures the pattern of recent outcomes, so the indexed counter can learn correlations in which the current branch depends on earlier ones. This is the basis of correlating or gshare predictors.

Question 48Computer Engineering (official domain breakdown not published in source)

Which condition makes a write-back cache with a write-allocate policy preferable to a write-through no-write-allocate cache?

  1. Writes are rare and reads dominate the workload
  2. The working set is much larger than the cache
  3. Repeated writes to the same block occur and the memory bus is a bottleneck Correct answer.
  4. Every write is immediately consumed by another bus master

Explanation

Write-back with write-allocate absorbs repeated writes in the cache and defers memory traffic until eviction, reducing bus utilization when the same block is rewritten. This is most valuable when bus bandwidth is scarce.

Question 49Computer Engineering (official domain breakdown not published in source)

A system must guarantee that a DMA transfer and the CPU never access the same memory buffer simultaneously. Which mechanism enforces this?

  1. The DMA controller writes only to cache, never to memory
  2. The CPU disables its clock for the duration of the transfer
  3. The operating system lower the bus frequency during transfers
  4. The DMA controller asserts bus ownership and the CPU is held off until the transfer completes Correct answer.

Explanation

The DMA controller becomes bus master and the CPU is prevented from driving the bus until the transfer finishes, avoiding conflicting accesses. This arbitration is typically handled by the memory or bus controller.

Question 50Computer Engineering (official domain breakdown not published in source)

In the IEEE 754 single-precision format, how many bits are allocated to the exponent field?

  1. 23
  2. 7
  3. 11
  4. 8 Correct answer.

Explanation

Single precision uses 1 sign bit, 8 exponent bits, and 23 fraction bits for a total of 32 bits. The exponent is biased by 127 so that both very large and very small magnitudes can be represented.