PE Computer Engineering cheat sheet

Amdahl's law: speedup = 1 / ((1 - f) + f/s), where f is the fraction enhanced and s the enhancement factor; the serial fraction caps speedup regardless of s.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) for a mixed instruction stream.

MIPS = clock rate (MHz) / CPI; MIPS is misleading across ISAs because instruction counts differ for the same program.

Memory hierarchy latency order: registers < L1 < L2 < L3 < main memory < SSD < magnetic disk < tape; each level trades capacity and cost per bit for speed.

Cache average access time = hit time + miss rate × miss penalty; AMAT is reduced by lowering any of the three terms.

Little's law: concurrency = arrival rate × average time in system; applies to pipelines, queues, and I/O subsystems.

Virtual memory: page table maps virtual to physical page numbers; TLB caches recent translations; a TLB miss followed by a page-table miss triggers a page fault.

RISC vs CISC decision rule: fixed-length instructions and load/store architecture favor pipelining; variable-length decoding favors code density.

Reliability: system availability = MTBF / (MTBF + MTTR); series components multiply availabilities, redundancy raises it.

Boolean identities: A + A'B = A + B (absorption); A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh map rule: group 1s in powers of two (1, 2, 4, 8), groups may wrap edges, and each group eliminates the variables that change within it.

Sum-of-products from a truth table: one minterm per output-1 row, OR them; product-of-sums uses maxterms from output-0 rows.

Two's complement: negate by inverting bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable before the clock edge for t_setup and after it for t_hold; max clock frequency is limited by combinational delay plus t_setup plus clock skew.

A D flip-flop samples D on the active edge; a latch is level-sensitive. Synchronous designs use edge-triggered flip-flops to avoid race conditions.

Finite state machine design: state diagram → state table → state assignment → next-state and output logic → implementation with flip-flops and combinational logic.

A multiplexer with n select lines implements any Boolean function of n variables by tying inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P for a control-flow graph; equivalently number of decision points + 1; it equals the minimum number of independent paths.

Test coverage hierarchy: statement < branch/decision < condition < path coverage; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box uses code structure.

Waterfall suits stable, well-understood requirements; iterative/agile suits evolving requirements with frequent deliverable increments.

Version control branching rule: feature branches isolate work; merges require conflict resolution; tags mark immutable releases.

Cohesion should be high (single responsibility) and coupling low (few inter-module dependencies); these are the standard design quality metrics.

Defect cost grows with the phase in which it is found; requirements and design defects are the most expensive to fix late.

Regression testing re-runs existing tests after a change to detect unintended breakage; it is distinct from acceptance testing, which validates fitness for use.

OSI layers (1-7): Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses to Link, Internet, Transport, Application.

IPv4 header is 20 bytes minimum; TTL decrements per router hop and prevents loops; the protocol field identifies the payload (6 = TCP, 17 = UDP, 1 = ICMP).

Subnetting: usable hosts per subnet = 2^h - 2 where h is host bits; /24 gives 254 usable addresses; /30 gives 2, used for point-to-point links.

TCP is connection-oriented with a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Ethernet CSMA/CD applies to half-duplex shared media; switched full-duplex links do not collide, so CSMA/CD is effectively obsolete there.

Private address ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT translates them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist for a noiseless channel is 2B log2(M) bits/s for M signal levels.

Routing decision rule: longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes from different sources.

Interrupt latency is the time from interrupt assertion to the first instruction of the handler; it includes context save and vector fetch, and bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it within a set interval; it is a recovery mechanism, not a correctness guarantee.

Volatile memory loses contents without power (SRAM, DRAM); non-volatile retains it (flash, EEPROM, FRAM); flash requires block erase before write.

Polling versus interrupts: polling is simpler and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O assigns device registers to addresses; port-mapped I/O uses a separate address space with dedicated instructions.

DMA transfers data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses two wires (SDA, SCL) with 7-bit addressing; SPI uses four wires (MOSI, MISO, SCLK, CS) and is full-duplex and faster; UART is asynchronous point-to-point.

Power: P ≈ C × V^2 × f for CMOS dynamic power; halving supply voltage quarters dynamic power, so voltage scaling is the dominant low-power lever.

Real-time systems: hard deadlines must never be missed; RMS assigns higher priority to shorter periods; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.

Amdahl's law: speedup = 1 / ((1 - f) + f/s), where f is the enhanced fraction and s the speedup of that fraction; the unenhanced fraction caps total gain.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) over the instruction mix.

MIPS = clock rate (MHz) / CPI; comparing MIPS across different ISAs is invalid because instruction counts per program differ.

Cache AMAT = hit time + miss rate × miss penalty; all three terms are independent levers for improving average memory latency.

Virtual memory: a TLB caches page-table translations; a TLB miss followed by a page-table miss raises a page fault handled by the OS.

Little's law: concurrency = arrival rate × average time in system; it bounds pipeline and queue occupancy.

RISC (fixed-length, load/store) favors deep pipelining; CISC (variable-length) favors code density and fewer instructions per operation.

Availability = MTBF / (MTBF + MTTR); series components multiply availabilities, while redundancy raises the composite value.

Absorption: A + A'B = A + B; A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh grouping: groups of 1, 2, 4, 8 cells; wrap across edges; each group removes the variables that change within it.

Sum-of-products uses minterms for output-1 rows; product-of-sums uses maxterms for output-0 rows.

Two's complement: negate by inverting all bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable t_setup before and t_hold after the active clock edge; max frequency is bounded by combinational delay + t_setup + skew.

An edge-triggered D flip-flop samples D on the active edge; a latch is level-sensitive and is avoided in synchronous design to prevent races.

FSM design flow: state diagram → state table → state assignment → next-state and output logic → implementation with flip-flops and gates.

An n-select multiplexer implements any Boolean function of n variables by tying its data inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P on a control-flow graph; equals decision points + 1 and the minimum number of independent paths.

Coverage hierarchy: statement < branch/decision < condition < path; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box techniques use code structure.

Waterfall fits stable requirements; iterative/agile fits evolving requirements delivered in increments.

Design quality: aim for high cohesion (single responsibility) and low coupling (few inter-module dependencies).

Defect cost rises with the phase of discovery; requirements and design defects are the most expensive to correct late.

Regression testing re-runs existing tests after a change; acceptance testing validates fitness for use by the customer.

Version control: feature branches isolate work, merges resolve conflicts, and tags mark immutable release points.

OSI layers 1-7: Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses these to Link, Internet, Transport, Application.

IPv4 header is at least 20 bytes; TTL decrements per hop and prevents loops; protocol 6 = TCP, 17 = UDP, 1 = ICMP.

Usable hosts per subnet = 2^h - 2 for h host bits; /24 yields 254 hosts; /30 yields 2 and is used for point-to-point links.

TCP uses a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT maps them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist noiseless capacity is 2B log2(M) bits/s for M signal levels.

Routing: the longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes.

CSMA/CD governs half-duplex shared Ethernet; switched full-duplex links do not collide, so it is effectively unused there.

Interrupt latency spans interrupt assertion to the first handler instruction, including context save and vector fetch; it bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it in time; it provides recovery, not correctness.

Volatile memory (SRAM, DRAM) loses contents without power; non-volatile memory (flash, EEPROM) retains it; flash requires block erase before write.

Polling is simple and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O places device registers in the address space; port-mapped I/O uses a separate space with dedicated instructions.

DMA moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses SDA and SCL with 7-bit addressing; SPI uses MOSI, MISO, SCLK, CS and is full-duplex and faster; UART is asynchronous point-to-point.

CMOS dynamic power P ≈ C × V^2 × f; halving supply voltage quarters dynamic power, making voltage scaling the dominant low-power lever.

Hard real-time deadlines must never be missed; rate-monotonic scheduling gives shorter-period tasks higher priority; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.

Amdahl's law: speedup = 1 / ((1 - f) + f/s); the unenhanced fraction (1 - f) limits the maximum gain no matter how large s becomes.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) across the instruction mix.

MIPS = clock rate (MHz) / CPI; cross-ISA MIPS comparisons are invalid because instruction counts per program differ.

Cache AMAT = hit time + miss rate × miss penalty; each term is an independent optimization target.

Virtual memory: the TLB caches page-table translations; a TLB miss followed by a page-table miss raises a page fault handled by the OS.

Little's law: concurrency = arrival rate × average time in system; it bounds pipeline occupancy and queue depth.

RISC (fixed-length, load/store) favors deep pipelining; CISC (variable-length) favors code density.

Availability = MTBF / (MTBF + MTTR); series components multiply availabilities, while redundancy raises the composite value.

Absorption: A + A'B = A + B and A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh grouping: groups of 1, 2, 4, or 8 cells; groups may wrap across edges; each group eliminates the variables that change within it.

Sum-of-products ORs minterms from output-1 rows; product-of-sums ANDs maxterms from output-0 rows.

Two's complement: negate by inverting all bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable t_setup before and t_hold after the active clock edge; maximum frequency is bounded by combinational delay + t_setup + skew.

An edge-triggered D flip-flop samples D on the active edge; a level-sensitive latch is avoided in synchronous designs to prevent races.

FSM design flow: state diagram → state table → state assignment → next-state and output logic → flip-flop and gate implementation.

An n-select multiplexer implements any Boolean function of n variables by tying its data inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P on a control-flow graph; it equals decision points + 1 and the minimum number of independent paths.

Coverage hierarchy: statement < branch/decision < condition < path; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box techniques use code structure.

Waterfall suits stable requirements; iterative and agile approaches suit evolving requirements delivered in increments.

Design quality: high cohesion (single responsibility) and low coupling (few inter-module dependencies) are the standard targets.

Defect cost rises with the phase of discovery; requirements and design defects are the most expensive to fix late.

Regression testing re-runs existing tests after a change; acceptance testing validates fitness for use by the customer.

Version control: feature branches isolate work, merges resolve conflicts, and tags mark immutable release points.

OSI layers 1-7: Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses these to Link, Internet, Transport, Application.

IPv4 header is at least 20 bytes; TTL decrements per hop and prevents loops; protocol 6 = TCP, 17 = UDP, 1 = ICMP.

Usable hosts per subnet = 2^h - 2 for h host bits; /24 yields 254 hosts; /30 yields 2 and is used for point-to-point links.

TCP uses a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT maps them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist noiseless capacity is 2B log2(M) bits/s for M signal levels.

Routing: the longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes.

CSMA/CD governs half-duplex shared Ethernet; switched full-duplex links do not collide, so it is effectively unused there.

Interrupt latency spans interrupt assertion to the first handler instruction, including context save and vector fetch; it bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it in time; it provides recovery, not correctness.

Volatile memory (SRAM, DRAM) loses contents without power; non-volatile memory (flash, EEPROM) retains it; flash requires block erase before write.

Polling is simple and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O places device registers in the address space; port-mapped I/O uses a separate space with dedicated instructions.

DMA moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses SDA and SCL with 7-bit addressing; SPI uses MOSI, MISO, SCLK, CS and is full-duplex and faster; UART is asynchronous point-to-point.

CMOS dynamic power P ≈ C × V^2 × f; halving supply voltage quarters dynamic power, making voltage scaling the dominant low-power lever.

Hard real-time deadlines must never be missed; rate-monotonic scheduling gives shorter-period tasks higher priority; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.

Amdahl's law: speedup = 1 / ((1 - f) + f/s); the unenhanced fraction (1 - f) limits the maximum gain no matter how large s becomes.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) across the instruction mix.

MIPS = clock rate (MHz) / CPI; cross-ISA MIPS comparisons are invalid because instruction counts per program differ.

Cache AMAT = hit time + miss rate × miss penalty; each term is an independent optimization target.

Virtual memory: the TLB caches page-table translations; a TLB miss followed by a page-table miss raises a page fault handled by the OS.

Little's law: concurrency = arrival rate × average time in system; it bounds pipeline occupancy and queue depth.

RISC (fixed-length, load/store) favors deep pipelining; CISC (variable-length) favors code density.

Availability = MTBF / (MTBF + MTTR); series components multiply availabilities, while redundancy raises the composite value.

Absorption: A + A'B = A + B and A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh grouping: groups of 1, 2, 4, or 8 cells; groups may wrap across edges; each group eliminates the variables that change within it.

Sum-of-products ORs minterms from output-1 rows; product-of-sums ANDs maxterms from output-0 rows.

Two's complement: negate by inverting all bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable t_setup before and t_hold after the active clock edge; maximum frequency is bounded by combinational delay + t_setup + skew.

An edge-triggered D flip-flop samples D on the active edge; a level-sensitive latch is avoided in synchronous designs to prevent races.

FSM design flow: state diagram → state table → state assignment → next-state and output logic → flip-flop and gate implementation.

An n-select multiplexer implements any Boolean function of n variables by tying its data inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P on a control-flow graph; it equals decision points + 1 and the minimum number of independent paths.

Coverage hierarchy: statement < branch/decision < condition < path; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box techniques use code structure.

Waterfall suits stable requirements; iterative and agile approaches suit evolving requirements delivered in increments.

Design quality: high cohesion (single responsibility) and low coupling (few inter-module dependencies) are the standard targets.

Defect cost rises with the phase of discovery; requirements and design defects are the most expensive to fix late.

Regression testing re-runs existing tests after a change; acceptance testing validates fitness for use by the customer.

Version control: feature branches isolate work, merges resolve conflicts, and tags mark immutable release points.

OSI layers 1-7: Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses these to Link, Internet, Transport, Application.

IPv4 header is at least 20 bytes; TTL decrements per hop and prevents loops; protocol 6 = TCP, 17 = UDP, 1 = ICMP.

Usable hosts per subnet = 2^h - 2 for h host bits; /24 yields 254 hosts; /30 yields 2 and is used for point-to-point links.

TCP uses a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT maps them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist noiseless capacity is 2B log2(M) bits/s for M signal levels.

Routing: the longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes.

CSMA/CD governs half-duplex shared Ethernet; switched full-duplex links do not collide, so it is effectively unused there.

Interrupt latency spans interrupt assertion to the first handler instruction, including context save and vector fetch; it bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it in time; it provides recovery, not correctness.

Volatile memory (SRAM, DRAM) loses contents without power; non-volatile memory (flash, EEPROM) retains it; flash requires block erase before write.

Polling is simple and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O places device registers in the address space; port-mapped I/O uses a separate space with dedicated instructions.

DMA moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses SDA and SCL with 7-bit addressing; SPI uses MOSI, MISO, SCLK, CS and is full-duplex and faster; UART is asynchronous point-to-point.

CMOS dynamic power P ≈ C × V^2 × f; halving supply voltage quarters dynamic power, making voltage scaling the dominant low-power lever.

Hard real-time deadlines must never be missed; rate-monotonic scheduling gives shorter-period tasks higher priority; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.

Amdahl's law: speedup = 1 / ((1 - f) + f/s); the unenhanced fraction (1 - f) limits the maximum gain no matter how large s becomes.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) across the instruction mix.

MIPS = clock rate (MHz) / CPI; cross-ISA MIPS comparisons are invalid because instruction counts per program differ.

Cache AMAT = hit time + miss rate × miss penalty; each term is an independent optimization target.

Virtual memory: the TLB caches page-table translations; a TLB miss followed by a page-table miss raises a page fault handled by the OS.

Little's law: concurrency = arrival rate × average time in system; it bounds pipeline occupancy and queue depth.

RISC (fixed-length, load/store) favors deep pipelining; CISC (variable-length) favors code density.

Availability = MTBF / (MTBF + MTTR); series components multiply availabilities, while redundancy raises the composite value.

Absorption: A + A'B = A + B and A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh grouping: groups of 1, 2, 4, or 8 cells; groups may wrap across edges; each group eliminates the variables that change within it.

Sum-of-products ORs minterms from output-1 rows; product-of-sums ANDs maxterms from output-0 rows.

Two's complement: negate by inverting all bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable t_setup before and t_hold after the active clock edge; maximum frequency is bounded by combinational delay + t_setup + skew.

An edge-triggered D flip-flop samples D on the active edge; a level-sensitive latch is avoided in synchronous designs to prevent races.

FSM design flow: state diagram → state table → state assignment → next-state and output logic → flip-flop and gate implementation.

An n-select multiplexer implements any Boolean function of n variables by tying its data inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P on a control-flow graph; it equals decision points + 1 and the minimum number of independent paths.

Coverage hierarchy: statement < branch/decision < condition < path; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box techniques use code structure.

Waterfall suits stable requirements; iterative and agile approaches suit evolving requirements delivered in increments.

Design quality: high cohesion (single responsibility) and low coupling (few inter-module dependencies) are the standard targets.

Defect cost rises with the phase of discovery; requirements and design defects are the most expensive to fix late.

Regression testing re-runs existing tests after a change; acceptance testing validates fitness for use by the customer.

Version control: feature branches isolate work, merges resolve conflicts, and tags mark immutable release points.

OSI layers 1-7: Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses these to Link, Internet, Transport, Application.

IPv4 header is at least 20 bytes; TTL decrements per hop and prevents loops; protocol 6 = TCP, 17 = UDP, 1 = ICMP.

Usable hosts per subnet = 2^h - 2 for h host bits; /24 yields 254 hosts; /30 yields 2 and is used for point-to-point links.

TCP uses a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT maps them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist noiseless capacity is 2B log2(M) bits/s for M signal levels.

Routing: the longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes.

CSMA/CD governs half-duplex shared Ethernet; switched full-duplex links do not collide, so it is effectively unused there.

Interrupt latency spans interrupt assertion to the first handler instruction, including context save and vector fetch; it bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it in time; it provides recovery, not correctness.

Volatile memory (SRAM, DRAM) loses contents without power; non-volatile memory (flash, EEPROM) retains it; flash requires block erase before write.

Polling is simple and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O places device registers in the address space; port-mapped I/O uses a separate space with dedicated instructions.

DMA moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses SDA and SCL with 7-bit addressing; SPI uses MOSI, MISO, SCLK, CS and is full-duplex and faster; UART is asynchronous point-to-point.

CMOS dynamic power P ≈ C × V^2 × f; halving supply voltage quarters dynamic power, making voltage scaling the dominant low-power lever.

Hard real-time deadlines must never be missed; rate-monotonic scheduling gives shorter-period tasks higher priority; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.

Amdahl's law: speedup = 1 / ((1 - f) + f/s); the unenhanced fraction (1 - f) limits the maximum gain no matter how large s becomes.

CPU time = instruction count × CPI × clock period; average CPI = Σ(CPI_i × instruction fraction_i) across the instruction mix.

MIPS = clock rate (MHz) / CPI; cross-ISA MIPS comparisons are invalid because instruction counts per program differ.

Cache AMAT = hit time + miss rate × miss penalty; each term is an independent optimization target.

Virtual memory: the TLB caches page-table translations; a TLB miss followed by a page-table miss raises a page fault handled by the OS.

Little's law: concurrency = arrival rate × average time in system; it bounds pipeline occupancy and queue depth.

RISC (fixed-length, load/store) favors deep pipelining; CISC (variable-length) favors code density.

Availability = MTBF / (MTBF + MTTR); series components multiply availabilities, while redundancy raises the composite value.

Absorption: A + A'B = A + B and A + AB = A; De Morgan: (AB)' = A' + B' and (A + B)' = A'B'.

Karnaugh grouping: groups of 1, 2, 4, or 8 cells; groups may wrap across edges; each group eliminates the variables that change within it.

Sum-of-products ORs minterms from output-1 rows; product-of-sums ANDs maxterms from output-0 rows.

Two's complement: negate by inverting all bits and adding 1; n-bit range is -2^(n-1) to 2^(n-1) - 1; subtraction is addition of the negated operand.

Setup/hold rule: data must be stable t_setup before and t_hold after the active clock edge; maximum frequency is bounded by combinational delay + t_setup + skew.

An edge-triggered D flip-flop samples D on the active edge; a level-sensitive latch is avoided in synchronous designs to prevent races.

FSM design flow: state diagram → state table → state assignment → next-state and output logic → flip-flop and gate implementation.

An n-select multiplexer implements any Boolean function of n variables by tying its data inputs to 0 or 1.

Cyclomatic complexity V(G) = E - N + 2P on a control-flow graph; it equals decision points + 1 and the minimum number of independent paths.

Coverage hierarchy: statement < branch/decision < condition < path; branch coverage subsumes statement coverage.

Black-box techniques: equivalence partitioning, boundary value analysis, decision tables, state transition testing; white-box techniques use code structure.

Waterfall suits stable requirements; iterative and agile approaches suit evolving requirements delivered in increments.

Design quality: high cohesion (single responsibility) and low coupling (few inter-module dependencies) are the standard targets.

Defect cost rises with the phase of discovery; requirements and design defects are the most expensive to fix late.

Regression testing re-runs existing tests after a change; acceptance testing validates fitness for use by the customer.

Version control: feature branches isolate work, merges resolve conflicts, and tags mark immutable release points.

OSI layers 1-7: Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP collapses these to Link, Internet, Transport, Application.

IPv4 header is at least 20 bytes; TTL decrements per hop and prevents loops; protocol 6 = TCP, 17 = UDP, 1 = ICMP.

Usable hosts per subnet = 2^h - 2 for h host bits; /24 yields 254 hosts; /30 yields 2 and is used for point-to-point links.

TCP uses a three-way handshake (SYN, SYN-ACK, ACK), sliding-window flow control, and retransmission; UDP is connectionless with no delivery guarantee.

Private ranges: 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; NAT maps them to public addresses at the boundary.

Shannon capacity C = B log2(1 + S/N); Nyquist noiseless capacity is 2B log2(M) bits/s for M signal levels.

Routing: the longest-prefix match wins; administrative distance or metric breaks ties among equal prefixes.

CSMA/CD governs half-duplex shared Ethernet; switched full-duplex links do not collide, so it is effectively unused there.

Interrupt latency spans interrupt assertion to the first handler instruction, including context save and vector fetch; it bounds real-time response.

A watchdog timer resets the processor if software fails to refresh it in time; it provides recovery, not correctness.

Volatile memory (SRAM, DRAM) loses contents without power; non-volatile memory (flash, EEPROM) retains it; flash requires block erase before write.

Polling is simple and deterministic but wastes cycles; interrupts free the CPU but add latency and concurrency hazards.

Memory-mapped I/O places device registers in the address space; port-mapped I/O uses a separate space with dedicated instructions.

DMA moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C uses SDA and SCL with 7-bit addressing; SPI uses MOSI, MISO, SCLK, CS and is full-duplex and faster; UART is asynchronous point-to-point.

CMOS dynamic power P ≈ C × V^2 × f; halving supply voltage quarters dynamic power, making voltage scaling the dominant low-power lever.

Hard real-time deadlines must never be missed; rate-monotonic scheduling gives shorter-period tasks higher priority; EDF is optimal for preemptive uniprocessor scheduling when utilization ≤ 100%.