PE Computer Engineering study plan

Map the Computer Systems blueprint into a one-page checklist of subtopics, marking each as known, shaky, or unknown

Derive cache hit/miss behavior by hand for a direct-mapped and a 2-way set-associative cache given an address trace

Compute average memory access time for three cache configurations and state which parameter dominates

Convert between binary, hex, and two's-complement representations for 8-, 16-, and 32-bit signed values

Sketch the datapath stages of a simple pipelined CPU and label where each hazard type arises

Explain virtual memory translation from virtual address to physical address including TLB, page table walk, and page fault path

Compare interrupt-driven I/O, DMA, and programmed I/O for a given throughput requirement and justify a choice

Minimize a 4-variable Boolean function using Karnaugh maps and verify the result algebraically

Design a combinational circuit from a truth table and express it in sum-of-products and product-of-sums form

Analyze a synchronous sequential circuit by deriving its state table and state diagram from a schematic description

Trace instruction execution through a 5-stage pipeline and quantify stall cycles for data, control, and structural hazards

Compute speedup and efficiency for a pipeline versus a non-pipelined datapath at several instruction mixes

Distinguish setup time, hold time, and propagation delay and check a given timing path against a clock constraint

Classify memory types (SRAM, DRAM, flash, EEPROM) by volatility, endurance, and typical embedded use

Select an appropriate communication bus (I2C, SPI, UART, CAN) for three stated embedded scenarios and defend each choice

Implement a bounded-buffer producer-consumer in a language of your choice using a mutex and condition variable, then remove the lock and demonstrate a race

Identify deadlock conditions in a supplied resource-allocation description and propose two distinct fixes

Write unit tests that achieve branch coverage on a function with nested conditionals and report the coverage number

Explain the difference between a process and a thread and predict output ordering for a given concurrent program

Describe the embedded firmware boot sequence from reset vector through initialization to main loop

Apply each SOLID principle to refactor a poorly structured class and document the before/after design

Compare waterfall, iterative, and agile lifecycle models and match each to a stated project constraint

Produce a requirements specification for a small feature with testable acceptance criteria

Construct a control-flow graph for a function and compute cyclomatic complexity by two methods

Perform a code review of a supplied snippet and log at least six defects classified by severity

Work through the TCP three-way handshake and connection teardown, labeling every flag and state transition

Compare TCP and UDP for four application profiles and justify the transport choice for each

Subnet a given IPv4 address space to satisfy stated host-count requirements and verify no overlap

Trace a packet across a routed network hop by hop, stating what changes in the headers at each device

Explain ARP, DNS resolution, and DHCP lease acquisition as ordered message sequences

Compute link budget or throughput for a given channel specification and identify the limiting factor

Describe the OSI and TCP/IP layer models and map five protocols to their layers with justification

Analyze an embedded networked device for security weaknesses at each layer and propose mitigations

Compare wired and wireless embedded networking options for latency, power, and range

Diagnose a described network failure using a structured layer-by-layer troubleshooting method

Take two full-length timed practice exams under exam conditions and record per-domain scores

Rank your five domains by accuracy and re-drill the two weakest with targeted problem sets

Rebuild your one-page checklist from week 1 and confirm every item is now marked known

Memorize and rehearse the standard formulas (AMAT, speedup, subnetting, complexity, link budget) from a single formula sheet

Simulate exam pacing by allocating time per question and reviewing flagged items