PE Computer Engineering flashcards

33 cards. Read the term and the definition here. The deck at the top of this page is optional.

Amdahl's Law

Speedup equals 1 divided by (1 minus f) plus f divided by s, where f is the enhanced fraction and s the local speedup. The unenhanced fraction caps total gain.

CPI

Cycles per instruction: the average number of clock cycles each instruction takes. CPU time equals instruction count times CPI times clock period.

Cache AMAT

Average memory access time equals hit time plus miss rate times miss penalty. Reducing any of the three terms lowers average latency.

TLB

Translation lookaside buffer: a small fast cache of recent virtual-to-physical page translations. A TLB miss may require a page-table walk.

Little's Law

The average number of items in a system equals arrival rate times average time each item spends there. It bounds queue depth and pipeline occupancy.

RISC versus CISC

RISC uses fixed-length, load/store instructions favoring deep pipelines. CISC uses variable-length instructions favoring code density and complex operations.

Availability formula

Availability equals MTBF divided by MTBF plus MTTR. Series components multiply their availabilities; redundancy raises the composite result.

Two's complement

Negate a number by inverting all bits and adding one. An n-bit value ranges from minus 2 to the n minus 1 up to 2 to the n minus 1 minus 1.

De Morgan's laws

The complement of a product equals the sum of the complements, and the complement of a sum equals the product of the complements.

Karnaugh map grouping

Group adjacent 1 cells in powers of two, wrapping across edges. Each group eliminates the variables that change value within it.

Setup and hold time

Data must be stable t_setup before and t_hold after the active clock edge. Violating either causes metastability in the flip-flop.

D flip-flop

An edge-triggered storage element that samples input D on the active clock edge and holds the value until the next edge.

Multiplexer as logic

A multiplexer with n select lines implements any Boolean function of n variables by tying each data input to logic 0 or 1.

FSM design flow

State diagram, then state table, then state assignment, then next-state and output logic, then implementation with flip-flops and combinational gates.

Cyclomatic complexity

V(G) equals edges minus nodes plus twice the components in a control-flow graph. It also equals decision points plus one, the minimum independent paths.

Branch coverage

A metric requiring every decision outcome to be exercised at least once. It subsumes statement coverage because every branch contains statements.

Boundary value analysis

A black-box technique testing values at and just outside the edges of input ranges, where defects cluster, rather than testing only middle values.

Cohesion and coupling

Cohesion measures how focused a module is internally; coupling measures dependencies between modules. Good design maximizes cohesion and minimizes coupling.

Regression testing

Re-running existing tests after a change to confirm nothing previously working has broken. It is distinct from acceptance testing.

Waterfall model

A sequential process with distinct requirements, design, implementation, and test phases. It suits stable requirements but resists late change.

OSI layers

Physical, Data Link, Network, Transport, Session, Presentation, Application. TCP/IP collapses these into Link, Internet, Transport, and Application layers.

Subnet host count

Usable hosts equal 2 to the h minus 2, where h is the number of host bits. A /24 gives 254; a /30 gives 2.

TCP three-way handshake

The client sends SYN, the server replies SYN-ACK, and the client sends ACK. This establishes sequence numbers before data transfer begins.

Private IP ranges

10.0.0.0/8, 172.16.0.0/12, and 192.168.0.0/16 are non-routable private ranges, translated to public addresses by NAT at the network boundary.

Shannon capacity

Channel capacity equals bandwidth times log base 2 of one plus signal-to-noise ratio. It sets the maximum error-free data rate for a noisy channel.

Longest-prefix match

A router selects the route whose prefix most specifically matches the destination address. Administrative distance or metric breaks ties among equal prefixes.

IPv4 TTL field

Time to live: an 8-bit header field decremented by each router. Reaching zero discards the packet and prevents routing loops.

Interrupt latency

The time from interrupt assertion to the first instruction of the handler, including context save and vector fetch. It bounds real-time response.

Watchdog timer

A hardware timer that resets the processor if software fails to refresh it within a set interval, recovering from hangs rather than preventing them.

Memory-mapped I/O

Device registers occupy addresses in the normal memory space and are accessed with ordinary load and store instructions, unlike port-mapped I/O.

DMA

Direct memory access: a controller moves data between peripherals and memory without per-byte CPU involvement, raising throughput and freeing the core.

I2C versus SPI

I2C uses two wires with 7-bit addressing and shared bus arbitration. SPI uses four wires, is full-duplex, and generally runs faster.

CMOS dynamic power

Dynamic power approximately equals capacitance times supply voltage squared times frequency. Halving voltage quarters dynamic power, so voltage scaling dominates.