PE Computer Engineering common mistakes
PE Computer Engineering · Understand the traps and how to avoid them.
In a cache or pipeline question, applying a formula (AMAT, speedup, CPI) to the numbers as written without first converting all quantities to consistent units, so a miss penalty in nanoseconds is multiplied by a miss rate against a hit time in cycles.
Exam stems deliberately mix units (ns, cycles, MHz, bytes vs. words) to test dimensional reasoning, and candidates under time pressure pattern-match to a memorized formula and plug in numbers in the order they appear.
What to do instead
Before computing, write a one-line unit ledger: list each given value with its unit and convert everything to a single base (cycles and seconds) at the top of your scratch work. Then state the formula symbolically, substitute, and sanity-check the magnitude (a cache speedup should not exceed the miss-penalty ratio).
Treating a pipelined processor's throughput as if it equaled 1/cycle with no stalls, ignoring data hazards, load-use latency, and branch penalties when asked for sustained IPC or execution time over a loop.
Textbook single-instruction latency diagrams make the pipeline look ideal, and candidates conflate latency of one instruction with steady-state throughput of a stream.
What to do instead
For loop or stream questions, count dynamic instructions, then add explicit stall cycles per iteration for each dependency class (load-use, ALU-to-branch, taken branch). Compute cycles = base cycles + stalls, and only then divide instructions by cycles for IPC.
Answering a virtual memory question by giving the page offset size from the virtual address and reusing it for the physical address, or forgetting that the TLB lookup and page-table walk happen in parallel with cache indexing.
Virtual and physical addresses frequently share offset width, so the numbers look interchangeable, and the TLB/cache interaction is taught as a diagram rather than a timing relationship.
What to do instead
Always derive the offset from the page size (log2 of page size) and state that it is identical in virtual and physical addresses; derive VPN and PFN widths separately from the address widths. For timing, draw the critical path explicitly: TLB hit vs. miss, then cache hit vs. miss, and sum the worst case.
Minimizing a Boolean function with a Karnaugh map or algebraic manipulation and then presenting the result without checking for static-1 or static-0 hazards, or without confirming the implementation is in the requested gate family (NAND-only, two-level).
Minimization is drilled as the goal, while hazard-free design and gate-family constraints are treated as afterthoughts, and the exam asks for the smallest hazard-free or NAND-only form.
What to do instead
After minimizing, re-read the constraint line of the stem. If hazard-free is required, add the consensus term covering every adjacent pair of 1s in the map. If NAND-only is required, apply De Morgan to the two-level SOP and verify by evaluating the truth table at the transition input.
Designing a synchronous sequential circuit (counter, FSM) without deriving next-state logic from the actual flip-flop excitation table, instead assuming D-type behavior for JK or T flip-flops.
Most coursework and practice uses D flip-flops, so the excitation columns for JK and T are recalled imprecisely under exam pressure.
What to do instead
Write the excitation table for the specified flip-flop at the top of the answer before touching the state table, then fill the input columns row by row. Finish by simulating two or three state transitions by hand to confirm the derived logic reproduces the intended sequence, including the reset or unused-state behavior.
In a setup/hold timing question, computing the maximum clock frequency from the combinational delay only, omitting clock-to-Q, clock skew, and the hold-time check on the shortest path.
Setup analysis is the familiar case, so candidates stop after the setup inequality and never test the hold inequality, which is a separate constraint on the minimum delay path.
What to do instead
Write both inequalities explicitly: setup requires T ≥ t_cq + t_comb(max) + t_setup − skew, and hold requires t_cq + t_comb(min) ≥ t_hold + skew. Solve the setup inequality for maximum frequency and the hold inequality for the minimum combinational delay, and report both because the stem may ask which path fails.
Answering a software engineering process question (testing level, design pattern, refactoring, agile ceremony) by naming the artifact that sounds most rigorous rather than the one that matches the stated defect type or lifecycle phase.
These questions are vocabulary-heavy and the distractors are all real, plausible terms, so recognition memory substitutes for reasoning about which term fits the scenario described.
What to do instead
Extract the scenario's key nouns first: what is being tested (unit, integration, system, acceptance), what property is at stake (behavior vs. structure), and at which phase. Then map to the term whose definition matches all three. If two options survive, choose the one that is cheapest to apply at that phase.
Describing a concurrency or data-structure answer without stating the invariant or the failure interleaving, so the answer asserts 'use a mutex' or 'use a hash map' without addressing the specific race, deadlock, or complexity requirement in the stem.
Candidates default to the safest-sounding primitive and skip the step of identifying the shared state and the interleaving that breaks it, which is what the question is actually testing.
What to do instead
Name the shared resource, the invariant it must satisfy, and one concrete interleaving that violates it. Then justify the chosen mechanism by showing it excludes that interleaving and note its cost (lock contention, memory overhead, worst-case complexity).
Computing subnet masks and host ranges by counting from a memorized /24 baseline and losing track of borrow bits, or forgetting to subtract the network and broadcast addresses when asked for usable hosts.
Subnetting is arithmetic under time pressure, and the common /24 anchor encourages mental shortcuts that break for non-octet-aligned prefixes such as /19 or /27.
What to do instead
Work in binary on paper: write the prefix, mark the boundary bit position, and derive the block size as 2^(32−prefix). List network address, first usable, last usable, and broadcast explicitly for each subnet, and state usable hosts as 2^h − 2 with the reason.
On an embedded question, proposing a polling or busy-wait design, or ignoring interrupt latency, priority inversion, and watchdog behavior, when the stem specifies real-time deadlines or low-power operation.
Simple polling loops are the first design taught and are easy to describe, but the exam scenario is constructed so that polling violates the stated deadline or power budget.
What to do instead
Check the stem for deadline, power, or concurrency keywords before choosing a mechanism. If real-time or low-power is stated, justify interrupts with sleep, quantify worst-case interrupt latency including the longest critical section, and address priority inversion with priority inheritance or ceiling protocols. Mention watchdog reset behavior for fault recovery.