PE Computer Engineering key terms

A small, fast memory between the CPU and main memory that holds recently used data and instructions. It reduces average access time because most programs reuse nearby data repeatedly.

The layered arrangement of storage, from fast expensive registers and caches to slower cheap main memory and disk. Each level trades capacity against latency, and data migrates between levels automatically.

The tendency of programs to access a small set of addresses repeatedly (temporal locality) and nearby addresses in sequence (spatial locality). Caches and prefetchers exploit this behavior to hide memory latency.

Overlapping the stages of instruction execution so several instructions are in flight at once. Throughput rises toward one instruction per cycle, though hazards and pipeline depth limit the gain.

A processor that can issue and execute multiple independent instructions per clock cycle using several functional units. Hardware scheduling and dependency checking decide which instructions can proceed together.

The degree to which instructions in a program stream can be executed simultaneously without changing the result. Compilers and hardware both exploit it through scheduling, pipelining, and multiple issue.

A condition where the next instruction cannot execute in its scheduled cycle because of a resource conflict, a data dependency, or a branch. Hardware stalls, forwards results, or predicts to mitigate it.

A technique where the processor guesses whether a branch is taken and the target address before the condition is known. Correct guesses keep the pipeline full; mispredictions flush and refill it.

An abstraction giving each process a private, contiguous address space mapped to physical frames by the memory management unit. It provides isolation, simplifies allocation, and enables paging to disk.

A per-process data structure mapping virtual page numbers to physical frame numbers and holding permission bits. The memory management unit walks it on a miss to translate addresses.

A small associative cache of recent virtual-to-physical address translations. A TLB hit avoids walking the page table, so its hit rate strongly affects memory access latency.

A formula bounding the speedup from improving part of a system: speedup is limited by the fraction of work that remains serial. It explains why parallel scaling saturates quickly.

Digital circuitry whose outputs depend only on the current inputs, with no stored state. Adders, multiplexers, and decoders are typical examples built from gates.

Digital circuitry whose outputs depend on current inputs and stored past values. Flip-flops and registers provide the memory that distinguishes it from purely combinational circuits.

A bistable storage element holding one bit, updated on a clock edge or level. It forms the basis of registers, counters, and state machines in synchronous designs.

The intervals before and after a clock edge during which a flip-flop's data input must stay stable. Violating them causes metastability, so timing analysis checks these constraints across all paths.

The difference in arrival time of the same clock edge at different registers. Excessive skew eats timing margin and can cause hold violations or functional failure in synchronous circuits.

A method that checks all timing paths in a design against clock constraints without simulation. It reports setup and hold slack and identifies critical paths before fabrication.

A grid layout of a truth table arranged so adjacent cells differ in one variable. Grouping adjacent ones yields simplified sum-of-products expressions for small Boolean functions.

The algebra of two-valued variables with AND, OR, and NOT operations and identities such as distributivity and De Morgan's laws. It is used to simplify and prove equivalence of logic expressions.

A model with a finite set of states, transitions triggered by inputs, and outputs. Mealy outputs depend on state and input; Moore outputs depend on state alone.

The longest delay path through a combinational circuit between registers or inputs and outputs. It sets the maximum clock frequency at which the design can operate reliably.

Transient wrong outputs caused by unequal path delays in combinational logic when inputs change. They are removed with redundant logic terms, careful state encoding, or synchronous sampling.

A defect where program correctness depends on the unpredictable interleaving of concurrent operations. It typically arises when shared data is accessed without proper synchronization.

Synchronization primitives controlling access to shared resources. A mutex enforces exclusive ownership by one thread; a counting semaphore permits a bounded number of concurrent holders or signals events.

A permanent stall where each process waits for a resource held by another in a cycle. It requires mutual exclusion, hold-and-wait, no preemption, and circular wait simultaneously.

An operation that executes indivisibly with respect to other threads, so no observer sees an intermediate state. Compare-and-swap and fetch-and-add are common hardware primitives for lock-free code.

A notation describing an upper bound on how an algorithm's cost grows with input size, ignoring constants. It characterizes scalability and guides selection among algorithms.

Measures of the running time and extra memory an algorithm requires as a function of input size. They let engineers compare algorithms independently of hardware and implementation details.

A data structure mapping keys to values via a hash function, giving average constant-time lookup. Collisions are resolved by chaining or open addressing, and load factor governs performance.

A tree where each node's left subtree holds smaller keys and right subtree larger keys. Search, insert, and delete cost proportional to height, which degrades to linear if unbalanced.

A technique where a function calls itself on smaller subproblems until reaching a base case. Each call consumes stack space, so depth and termination must be managed carefully.

A tool that records snapshots of source files and supports branching, merging, and history review. Distributed systems such as Git give each developer a full repository copy.

Automated tests that exercise individual functions or classes in isolation against expected results. They catch regressions early and support safe refactoring when run frequently.

A practice where developers merge small changes frequently and each merge triggers automated build and test runs. Failures surface quickly, keeping the mainline releasable.

A seven-layer conceptual framework describing network functions from physical signaling to applications. It separates concerns and lets protocols at one layer be replaced independently.

The practical protocol stack underlying the Internet, with link, internet, transport, and application layers. IP delivers packets; TCP and UDP provide distinct transport services above it.

Wrapping data with protocol headers as it passes down the stack, so each layer adds its own control information. The receiver strips headers in reverse order.

TCP offers connection setup, ordered reliable delivery, and flow control; UDP sends independent datagrams with no guarantees. TCP suits file transfer, UDP suits low-latency voice and video.

Dividing an IP address range into smaller networks and writing prefixes as address/length. Classless inter-domain routing aggregates routes and conserves address space.

Switching forwards frames within a local network using MAC addresses; routing forwards packets between networks using IP addresses and routing tables. Both rely on forwarding tables built dynamically or statically.

The arrangement of links and nodes in a network, such as star, bus, ring, mesh, or tree. Topology affects cost, fault tolerance, and performance.

Two ways a processor learns a device needs service. Polling repeatedly checks status at fixed intervals; interrupts signal the CPU asynchronously, saving cycles but adding handling overhead.

A controller that moves data between peripherals and memory without per-byte CPU involvement. The CPU sets up the transfer and is interrupted on completion, freeing it for other work.

An addressing scheme where device registers appear as memory locations, so ordinary load and store instructions access hardware. It simplifies programming but consumes address space.

An operating system designed to meet deterministic timing deadlines, not just average throughput. It provides priority scheduling and bounded latency for tasks with hard or soft deadlines.

A hardware counter that resets the system if software fails to service it within a set period. It recovers embedded devices from hangs and infinite loops.