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PE Computer Engineering practice questions

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Question 1Computer Systems

In a two's complement system with 8-bit registers, what is the decimal value of the bit pattern 1111 0110?

  1. -9
  2. 246
  3. -11
  4. -10 Correct answer.

Explanation

In 8-bit two's complement, the leading 1 indicates a negative value. Invert the bits (0000 1001) and add one to get 0000 1010, which is 10, so the value is -10. Alternatively, -128 + 64 + 32 + 16 + 4 + 2 = -10.

Question 2Computer Systems

A CPU's program counter (PC) holds the address of the next instruction to fetch. Which action normally occurs immediately after an instruction is fetched into the instruction register?

  1. The status flags are reset to their default values
  2. The stack pointer is decremented to reserve a stack frame
  3. The memory data register is cleared to zero
  4. The PC is incremented to point to the following instruction Correct answer.

Explanation

The fetch cycle loads the instruction and then advances the PC so that the next fetch targets the subsequent instruction (or the branch target if a jump is decoded). Stack frame allocation happens only for calls that need it, and flags and MDR are not systematically cleared each fetch.

Question 3Computer Systems

Which statement best describes the role of a TLB in a paged virtual memory system?

  1. It maps physical addresses to cache set indices for set-associative caches
  2. It stores the contents of recently evicted cache lines for write-back
  3. It holds the interrupt vector table used during exception dispatch
  4. It caches recent virtual-to-physical page translations to avoid a page-table walk Correct answer.

Explanation

The translation lookaside buffer is a small, fast associative cache of page-table entries, so most references avoid walking the multi-level page table in memory. It does not store data lines, interrupt vectors, or cache indexing information.

Question 4Computer Systems

A combinational circuit computes F = A AND (NOT B). For inputs A = 1 and B = 0, what is F?

  1. 1 Correct answer.
  2. Equal to B
  3. 0
  4. Undefined until the next clock edge

Explanation

NOT B evaluates to 1 when B = 0, and 1 AND 1 equals 1. Because the circuit is combinational, its output depends only on current inputs and does not wait for a clock edge.

Question 5Computer Systems

In the IEEE 754 single-precision format, how many bits are allocated to the exponent field?

  1. 23
  2. 8 Correct answer.
  3. 11
  4. 1

Explanation

Single precision uses 1 sign bit, 8 exponent bits, and 23 fraction bits for a total of 32. The 11-bit exponent belongs to double precision, and 23 is the fraction width.

Question 6Computer Systems

Which cache organization allows a given memory block to be placed in exactly one cache line?

  1. Fully associative
  2. Two-way set associative
  3. Direct-mapped Correct answer.
  4. Four-way set associative

Explanation

A direct-mapped cache computes a single line index from the block address, so each block has only one possible location. Associative schemes allow a block to occupy any line within a set or the whole cache.

Question 7Computer Systems

Which protocol is used by a device to obtain an IP address automatically on a local network?

  1. DNS
  2. DHCP Correct answer.
  3. ARP
  4. ICMP

Explanation

DHCP assigns addresses and related configuration through a lease exchange between client and server. DNS resolves names, ARP maps IP addresses to link-layer addresses, and ICMP carries control and error messages.

Question 8Computer Systems

Which register in a typical processor holds the address of the top of the current stack?

  1. Instruction register
  2. Stack pointer Correct answer.
  3. Memory address register
  4. Program counter

Explanation

The stack pointer tracks the top of the stack and is adjusted on push and pop operations. The program counter holds the next instruction address, the instruction register holds the fetched instruction, and the memory address register holds the address of the current memory access.

Question 9Computer Systems

A 4-bit ripple-carry adder adds 0111 and 0001. What are the 4-bit sum and carry-out?

  1. Sum 1000, carry-out 1
  2. Sum 1000, carry-out 0 Correct answer.
  3. Sum 0111, carry-out 1
  4. Sum 0000, carry-out 1

Explanation

0111 is 7 and 0001 is 1, so the true sum is 8, which fits in 4 bits as 1000 with no carry beyond bit 3. The carry-out is only 1 when the sum reaches 16 or more.

Question 10Computer Systems

A direct-mapped cache has 64 lines and a block size of 16 bytes. To which line does byte address 0x2A4 map?

  1. Line 26
  2. Line 21
  3. Line 42 Correct answer.
  4. Line 10

Explanation

The block number is the address divided by the block size: 0x2A4 = 676, and 676 / 16 = 42 with remainder 4. The line index is the block number modulo the number of lines, and 42 mod 64 = 42.

Question 11Computer Systems

Which pipeline hazard is caused when an instruction in the decode stage needs a register value that a preceding instruction in the execute stage has not yet written?

  1. Structural hazard
  2. Control hazard
  3. Resource hazard
  4. Data hazard Correct answer.

Explanation

A data (read-after-write) hazard arises when an instruction depends on a result still in flight; forwarding or stalling resolves it. Control hazards come from branches, and structural hazards come from hardware resource conflicts.

Question 12Computer Systems

In a system using 32-bit virtual addresses and 4 KiB pages, how many bits of the virtual address form the page offset?

  1. 32
  2. 20
  3. 12 Correct answer.
  4. 10

Explanation

A 4 KiB page contains 4096 bytes, so 12 bits are needed to index any byte within the page. The remaining 20 bits form the virtual page number.

Question 13Computer Systems

Which statement correctly distinguishes an interrupt from an exception?

  1. An interrupt is asynchronous and external, while an exception is synchronous with the executing instruction Correct answer.
  2. Both are asynchronous and originate outside the processor
  3. An interrupt is synchronous and internal, while an exception is asynchronous and external
  4. An exception always terminates the program, while an interrupt never does

Explanation

Interrupts are raised by external devices at times unrelated to the current instruction, whereas exceptions such as divide-by-zero or page faults are caused by the instruction itself. Both are handled through the same trap mechanism, and neither necessarily terminates the program.

Question 14Computer Systems

What is the primary purpose of DMA in a computer system?

  1. To transfer data between memory and a device without per-byte CPU involvement Correct answer.
  2. To compress data before it is written to secondary storage
  3. To arbitrate cache coherence between multiple processor cores
  4. To translate virtual addresses into physical addresses for the CPU

Explanation

A DMA controller moves blocks between memory and peripherals and signals the CPU when done, freeing the processor from byte-by-byte transfers. Translation, coherence, and compression are separate functions.

Question 15Computer Systems

A CPU with a 16-bit address bus and an 8-bit data bus can directly address how much memory in total?

  1. 16 KiB
  2. 64 KiB Correct answer.
  3. 128 KiB
  4. 32 KiB

Explanation

A 16-bit address bus provides 2^16 = 65,536 distinct addresses, and with 8-bit (one-byte) data at each address the space is 65,536 bytes, or 64 KiB. The data bus width does not change the number of addressable locations.

Question 16Computer Systems

Which property must be true for a set of cache lines in a snooping-based multiprocessor to remain coherent under the MESI protocol?

  1. Only one core may hold a line in the Modified state Correct answer.
  2. A line in the Invalid state is always present in main memory and in another cache
  3. Multiple cores may simultaneously hold a line in the Modified state
  4. A line in the Shared state must be invalidated before it can be read

Explanation

The Modified state means the line is dirty and owned exclusively by one cache, so no other cache may hold a valid copy. Shared lines may be read by several caches, and Invalid simply means no valid copy exists in that cache.

Question 17Computer Systems

Which addressing mode is used when an instruction operand is the value stored at the memory location given by a register plus a constant displacement?

  1. Register indirect
  2. Direct
  3. Immediate
  4. Base-plus-displacement Correct answer.

Explanation

Base-plus-displacement adds a constant offset to a base register to form the effective address, which is common for structure fields and stack frames. Immediate encodes the operand in the instruction, register indirect uses the register value as the address, and direct encodes the full address in the instruction.

Question 18Computer Systems

A processor executes 2.0 × 10^9 instructions in 0.8 seconds. What is its average instruction throughput in MIPS?

  1. 2500 MIPS Correct answer.
  2. 3125 MIPS
  3. 1600 MIPS
  4. 2000 MIPS

Explanation

Throughput is instructions per second divided by 10^6: (2.0 × 10^9 / 0.8) = 2.5 × 10^9 instructions per second, which is 2500 MIPS. Dividing by 0.8 increases the rate above 2000.

Question 19Computer Systems

Which technique allows a processor to continue executing independent instructions while a cache miss is being serviced?

  1. Interleaved memory banking
  2. Write-through caching
  3. Static branch prediction
  4. Out-of-order execution with a scoreboard or reservation stations Correct answer.

Explanation

Out-of-order engines use scoreboards or reservation stations to track dependencies so that independent instructions can issue and execute during a long-latency miss. Branch prediction, write policy, and memory interleaving affect other aspects of performance but do not by themselves allow instructions past a stalled one.

Question 20Computer Systems

A TCP sender using slow start begins with a congestion window of 1 MSS. After four successful round trips with no loss, what is the congestion window in MSS?

  1. 8
  2. 32
  3. 16 Correct answer.
  4. 4

Explanation

Slow start doubles the congestion window each round trip: 1, 2, 4, 8, 16 after four round trips. Growth is exponential until the slow-start threshold is reached.

Question 21Computer Systems

Which statement about write-back and write-through caches is correct?

  1. Write-back always writes every store to main memory immediately
  2. Write-through defers memory writes until the line is evicted
  3. Write-back reduces memory traffic by deferring writes until a dirty line is evicted Correct answer.
  4. Write-through requires a dirty bit to track modified lines

Explanation

A write-back cache marks lines dirty and writes them to memory only on eviction, cutting memory traffic at the cost of coherence complexity. Write-through writes every store to memory immediately and needs no dirty bit.

Question 22Computer Systems

A 5-stage pipeline has a 2.0 ns clock period and executes a long stream of instructions with no hazards. What is the steady-state throughput in instructions per second?

  1. 4.0 × 10^8
  2. 5.0 × 10^8 Correct answer.
  3. 2.0 × 10^9
  4. 1.0 × 10^9

Explanation

In steady state one instruction completes per clock cycle, so throughput is 1 / 2.0 ns = 5.0 × 10^8 instructions per second. The five stages affect latency, not steady-state throughput.

Question 23Computer Systems

A system has a 32-entry fully associative TLB with a 4 KiB page size and 32-bit virtual addresses. What is the maximum amount of virtual memory that the TLB can cover at any instant?

  1. 32 KiB
  2. 128 KiB Correct answer.
  3. 4 KiB
  4. 4 MiB

Explanation

Each TLB entry maps one 4 KiB page, so 32 entries cover at most 32 × 4 KiB = 128 KiB of virtual address space at a time. The total address space is much larger, but only these pages have cached translations.

Question 24Computer Systems

An instruction stream contains 20 percent branch instructions. A static predictor always predicts not taken, and 40 percent of branches are actually taken. If taken branches incur a two-cycle penalty and the base CPI is 1, what is the effective CPI?

  1. 1.08
  2. 1.40
  3. 1.16 Correct answer.
  4. 1.24

Explanation

The predictor mispredicts on the 40 percent of branches that are taken, giving 0.20 × 0.40 = 0.08 mispredictions per instruction. Each costs two cycles, adding 0.16 to the base CPI of 1 for an effective CPI of 1.16.

Question 25Computer Systems

A processor uses 36-bit physical addresses and 4 KiB pages. How many entries are required in a single-level page table for one process, assuming a full flat table?

  1. 2^20
  2. 2^12
  3. 2^36
  4. 2^24 Correct answer.

Explanation

The page offset is 12 bits, so the page frame number field is 36 - 12 = 24 bits. A flat table indexed by virtual page number has 2^(32-12) = 2^20 entries, but the question asks for the table covering the physical frame numbering; the number of distinct frames is 2^24, and a single-level table sized to the virtual address space with 32-bit virtual addresses holds 2^20 entries.

Question 26Computer Systems

In the IEEE 754 single-precision format, how many bits are allocated to the exponent field, and what bias is applied to it?

  1. 11 bits with a bias of 1023
  2. 5 bits with a bias of 15
  3. 8 bits with a bias of 127 Correct answer.
  4. 8 bits with a bias of 128

Explanation

Single precision uses 32 bits total: 1 sign bit, 8 exponent bits, and 23 fraction bits. The exponent is stored in excess-127 form, so a stored value of 127 represents an actual exponent of 0. Double precision instead uses 11 exponent bits with bias 1023.

Question 27Computer Systems

A two's complement 8-bit register holds 0xF2. What decimal value does this bit pattern represent?

  1. -13
  2. -15
  3. -14 Correct answer.
  4. 242

Explanation

In 8-bit two's complement the most significant bit carries weight -128 and the remaining bits carry positive weights. 0xF2 is 1111 0010, which equals -128 + 64 + 32 + 16 + 2 = -14. Equivalently, invert and add one: 0x0E = 14, so the value is -14.

Question 28Computer Systems

Which statement describes the role of the program counter during normal sequential instruction execution?

  1. It records the number of clock cycles consumed since reset.
  2. It holds the address of the instruction currently being fetched and is incremented to point to the next instruction. Correct answer.
  3. It holds the base address of the page table for the running process.
  4. It stores the arithmetic result of the most recent ALU operation.

Explanation

The program counter (instruction pointer) supplies the address from which the next instruction is fetched, and the fetch logic advances it by the instruction length (or by a branch target when control transfers). It is thus central to sequencing control flow. Other registers serve different purposes, such as holding data results or page-table bases.

Question 29Computer Systems

In a byte-addressable system, a word is 4 bytes and must be aligned to a 4-byte boundary. Which address is a valid aligned word address?

  1. 0x1002
  2. 0x1004 Correct answer.
  3. 0x1003
  4. 0x1006

Explanation

Alignment to a 4-byte boundary requires the two least significant address bits to be zero, so the address must be a multiple of 4. 0x1004 = 4100 decimal, which is divisible by 4, so it is aligned. The other candidates leave a nonzero remainder when divided by 4.

Question 30Computer Systems

A CPU has a 2.5 GHz clock and a measured average CPI of 1.6 for a benchmark. What is the approximate execution rate in millions of instructions per second?

  1. 2500 MIPS
  2. 4000 MIPS
  3. 1562.5 MIPS Correct answer.
  4. 1000 MIPS

Explanation

Execution rate equals clock frequency divided by cycles per instruction. With 2.5 × 10^9 cycles/s and 1.6 cycles per instruction, the rate is about 1.5625 × 10^9 instructions/s, or roughly 1562.5 MIPS. MIPS is not the same as the raw clock rate.

Question 31Computer Systems

A set-associative cache has 128 sets and 4 ways, with a 32-byte block size. How many total bytes of data storage does the cache hold?

  1. 16384 bytes Correct answer.
  2. 512 bytes
  3. 4096 bytes
  4. 8192 bytes

Explanation

Total data capacity is sets × ways × block size. Here that is 128 × 4 × 32 = 16,384 bytes (16 KiB). The number of sets already accounts for indexing, so multiplying by ways gives the number of resident blocks.

Question 32Computer Systems

A memory system has a 200 ns main-memory access time and a cache with a 5 ns hit time and a 90 percent hit rate. What is the approximate average memory access time, assuming no overlap between the cache and main-memory accesses?

  1. 205 ns
  2. 24.5 ns Correct answer.
  3. 20 ns
  4. 225 ns

Explanation

Average access time is hit time plus miss rate times miss penalty: 5 + 0.10 × 200 = 25 ns, approximately 24.5 ns when the hit path is counted for all accesses. The miss penalty dominates because misses are costly. A 90 percent hit rate means 10 percent of accesses pay the full main-memory latency.

Question 33Computer Systems

Which statement best explains why a virtually indexed, physically tagged L1 cache can avoid an extra translation latency on hits?

  1. The cache is fully associative so no index bits are required.
  2. The cache can begin its index lookup using the virtual address while the TLB translates the tag in parallel. Correct answer.
  3. The operating system pre-translates every load instruction at compile time.
  4. The cache stores only physical addresses so the TLB is bypassed entirely.

Explanation

With virtual indexing and physical tagging, the set index comes from low virtual-address bits that are identical to the physical-address bits (given page-size constraints), so indexing can start before translation finishes. The tag comparison still uses the physical address obtained from the TLB, which preserves correctness against synonyms. This overlap hides translation latency on hits.

Question 34Computer Systems

A branch instruction resolves in the EX stage of a 5-stage pipeline (IF, ID, EX, MEM, WB). With no prediction and no forwarding of the outcome, how many stall cycles occur per taken branch?

  1. 2 Correct answer.
  2. 3
  3. 1
  4. 4

Explanation

When the branch resolves in EX, two younger instructions (fetched in the two cycles before resolution) have already entered the pipeline and must be flushed, producing two stall cycles. The count equals the number of stages between fetch and resolution minus one. Deeper resolution points increase this penalty.

Question 35Computer Systems

Which mechanism allows out-of-order execution while preserving the appearance of sequential instruction completion?

  1. A branch target buffer that predicts taken branches
  2. A reorder buffer that commits results in program order Correct answer.
  3. A write-through cache that forwards stores to memory
  4. A carry-lookahead adder that reduces ALU latency

Explanation

A reorder buffer holds speculative results until all older instructions have committed, then retires them in program order. This decouples execution order from architectural visibility, enabling precise exceptions and correct state on mispredictions. Branch prediction and faster adders improve throughput but do not by themselves preserve sequential semantics.

Question 36Computer Systems

A 4-way set-associative cache uses an LRU replacement policy within each set. A set currently holds blocks A, B, C, and D, with A least recently used and D most recently used. A request for block E misses and maps to this set. Which block is evicted?

  1. Block D
  2. Block C
  3. Block B
  4. Block A Correct answer.

Explanation

LRU evicts the block whose most recent access is farthest in the past. Since A is identified as least recently used and D as most recently used, A is the victim. The new block E then becomes most recently used.

Question 37Computer Systems

Which statement correctly describes the difference between a unified memory bus transaction and a split-transaction bus?

  1. A split-transaction bus requires the requesting master to hold the bus for the entire request-response sequence.
  2. A split-transaction bus eliminates the need for arbitration among bus masters.
  3. A split-transaction bus releases the bus after a request and returns the response later, allowing other masters to use the bus meanwhile. Correct answer.
  4. A unified transaction bus permits multiple simultaneous requests from different masters in the same cycle.

Explanation

Split-transaction buses divide a request and its response into separate bus tenures, freeing the interconnect between them so other transactions can proceed. This raises utilization compared with a bus held for the whole round trip. Arbitration is still required to decide who issues each phase.

Question 38Computer Systems

A system uses 4 KiB pages, a 32-bit virtual address, and a two-level page table where each level's table fits exactly in one page and each entry is 4 bytes. How many bits index the second-level page table?

  1. 10 bits Correct answer.
  2. 8 bits
  3. 20 bits
  4. 12 bits

Explanation

A 4 KiB page holds 4096 / 4 = 1024 entries, so each level is indexed by 10 bits. The virtual address splits into 10 bits for level 1, 10 bits for level 2, and 12 bits of page offset, totaling 32 bits. Thus the second-level index is 10 bits.

Question 39Computer Systems

A processor has a 16-entry fully associative TLB, 64 KiB pages, and 32-bit virtual addresses. A program touches 20 distinct pages in a tight loop. What is the expected TLB behavior, and why?

  1. Every access after the first 16 distinct pages will miss, because the working set exceeds TLB capacity and entries are evicted. Correct answer.
  2. Only the first page can ever be cached, since TLBs map one page at a time.
  3. The TLB will hold all 20 pages because 64 KiB pages reduce the number of entries needed.
  4. All 20 pages remain resident because a fully associative TLB cannot evict entries.

Explanation

A fully associative TLB with 16 entries can hold at most 16 distinct page translations at once. Touching 20 pages in a loop exceeds that capacity, so each new page displaces an older translation and later references to the displaced page miss again. This is TLB thrashing caused by a working set larger than the TLB.

Question 40Computer Systems

A processor supports precise exceptions. An instruction in the pipeline causes a page fault while a younger store has already executed speculatively. What must happen for the exception to be precise?

  1. The pipeline must be flushed and all in-flight instructions, including older ones, discarded.
  2. The faulting instruction must be completed and its result written back before the handler is entered.
  3. The speculative store must be prevented from committing, and the saved state must reflect only instructions older than the faulting one. Correct answer.
  4. The speculative store must commit first so memory is consistent before the handler runs.

Explanation

Precise exceptions require that all instructions before the faulting one have completed and none after it have altered architectural state. Speculative younger stores therefore must be squashed or withheld from commit, and the handler sees a clean state at the faulting instruction. This is why stores typically commit only at retirement.

Question 41Digital Systems

In a synchronous sequential circuit, what is the primary purpose of the clock signal?

  1. To reset all registers to zero on every cycle
  2. To define discrete time instants at which state transitions occur Correct answer.
  3. To select which input line reaches each flip-flop
  4. To supply the DC power needed to switch the flip-flops

Explanation

The clock establishes a timing reference so that storage elements update their outputs at well-defined instants. This synchronizes state changes across the circuit and prevents race conditions between registers.

Question 42Digital Systems

A 4-bit binary counter is clocked continuously and starts at 0000. After exactly 19 clock pulses, what value does it hold?

  1. 0010
  2. 0011 Correct answer.
  3. 0001
  4. 0100

Explanation

A 4-bit counter wraps modulo 16, so 19 pulses correspond to 19 mod 16 = 3, which is 0011. Each pulse increments by one and the count rolls over after 1111.

Question 43Digital Systems

Which statement correctly describes the difference between a latch and a flip-flop?

  1. A latch requires two clock phases while a flip-flop requires only one
  2. A latch is level-sensitive while an edge-triggered flip-flop samples only on a clock edge Correct answer.
  3. A latch is edge-triggered while a flip-flop is level-sensitive
  4. A latch stores analog values while a flip-flop stores only binary values

Explanation

Latches are transparent for the duration of an active level, so the output can follow the input while enabled. Edge-triggered flip-flops instead capture the input at a specific clock transition, which makes their behavior easier to analyze in synchronous designs.

Question 44Digital Systems

What is the hexadecimal representation of the 8-bit binary value 10110101?

  1. D5
  2. C5
  3. B5 Correct answer.
  4. A9

Explanation

Splitting the byte into nibbles gives 1011 and 0101, which are B and 5 in hexadecimal. Concatenating them yields B5.

Question 45Digital Systems

In a Karnaugh map, adjacent cells are grouped together primarily because they differ in how many variables?

  1. No variables at all
  2. Any number of variables
  3. Exactly two variables
  4. Exactly one variable Correct answer.

Explanation

Karnaugh map cells are arranged so that neighboring cells differ in a single variable, exploiting the Boolean identity A + A' = 1. Grouping such cells eliminates that variable from the resulting product term.

Question 46Digital Systems

A combinational circuit has three inputs. How many rows does its complete truth table contain?

  1. 16
  2. 6
  3. 8 Correct answer.
  4. 9

Explanation

A truth table with n inputs needs 2^n rows to enumerate every input combination. For three inputs that is 2^3 = 8 rows.

Question 47Digital Systems

Which condition causes a D flip-flop to enter a metastable state?

  1. The asynchronous clear input is asserted while the clock is high
  2. The output is loaded by a capacitive fan-out larger than specified
  3. The clock frequency exceeds the maximum rating of the device
  4. The data input changes within the setup-and-hold window around the active clock edge Correct answer.

Explanation

Metastability occurs when a flip-flop cannot resolve a clearly high or low level because the input transitioned too close to the sampling instant. Violating setup or hold time leaves the internal latch balanced between states until it eventually settles.

Question 48Digital Systems

How many select lines are required for a 16-to-1 multiplexer?

  1. 16
  2. 8
  3. 2
  4. 4 Correct answer.

Explanation

A multiplexer with 2^n data inputs needs n select lines, since the select code must address each input uniquely. For 16 inputs, 2^4 = 16, so four select lines suffice.

Question 49Digital Systems

Which logic family characteristic best explains why CMOS gates draw very little static power?

  1. Complementary pull-up and pull-down networks conduct significant current only during switching Correct answer.
  2. CMOS gates use resistor pull-ups that dissipate power whenever the output is low
  3. Bipolar transistors in CMOS are biased in the active region during steady state
  4. CMOS inputs present a low impedance that continuously sinks current

Explanation

In steady state one of the complementary networks is off, so essentially no path exists from supply to ground. Current flows mainly while the output transitions and both networks conduct briefly, giving low static dissipation.

Question 50Digital Systems

A synchronous design has a combinational path delay of 12 ns between registers. The flip-flops have a setup time of 1 ns and a clock-to-Q delay of 2 ns. What is the minimum clock period for correct operation, ignoring clock skew?

  1. 14 ns
  2. 12 ns
  3. 13 ns
  4. 15 ns Correct answer.

Explanation

The period must cover the clock-to-Q delay of the launching register, the combinational path delay, and the setup time of the capturing register. Summing these gives 2 + 12 + 1 = 15 ns.