Computer Systems
Computer Systems tests how architecture, the memory hierarchy, and operating-system mechanisms interact to determine performance. Expect quantitative questions on CPU time, cache behavior, pipelining, and virtual memory rather than definitions alone.
Performance equations
CPU time = instruction count × CPI × clock period. Speedup from an enhancement is bounded by the fraction improved: S = 1 / ((1 − f) + f/k), Amdahl’s law. Report units consistently: a 1 GHz clock has a 1 ns period, not 1 ps.
Memory hierarchy
Average memory access time (AMAT) = hit time + miss rate × miss penalty. Write-back caches need a dirty-bit writeback before eviction; write-through caches generate more bus traffic but simpler coherence. Virtual memory uses page tables and a TLB; a TLB miss may still hit in the page table, while a page fault requires storage I/O.
Pipeline hazards
Structural, data, and control hazards cause stalls. Forwarding removes many ALU-to-ALU dependences but not load-use latency. Branch prediction reduces control stalls; misprediction flushes the pipeline.
Worked example
A 3 GHz processor executes 2.0×10^9 instructions at CPI 1.5. Time = (2.0×10^9 × 1.5) / (3×10^9 s^−1) = 1.0 s. If 80% of that time is parallelizable and is sped up 4×, Amdahl gives S = 1/(0.2 + 0.8/4) = 1/0.4 = 2.5, so the new time is 0.40 s, not 0.25 s.
Traps
- Mixing cycle counts with nanoseconds in AMAT.
- Using the enhanced fraction in the wrong part of Amdahl’s denominator.
- Assuming a TLB miss always means a page fault.
- Forgetting that a load-use hazard may need a stall even with forwarding.