Digital Systems
Digital Systems tests combinational and sequential design, number representation, and static timing analysis. Questions often require a gate-level or timing-level calculation, not a verbal description.
Combinational logic
Use Karnaugh maps with don’t-care terms to minimize SOP/POS forms. Static-1 and static-0 hazards occur when a variable and its complement meet; add consensus terms or use synchronous registered outputs. Two’s-complement range for n bits is −2^(n−1) to 2^(n−1)−1; overflow occurs when adding same-sign operands gives the opposite sign.
Sequential logic and timing
For a positive-edge register path, setup requires Tclk ≥ t_cq + t_comb + t_setup + t_skew. Hold requires t_cq + t_comb ≥ t_hold + t_skew and is independent of clock period. Mealy outputs depend on inputs and state; Moore outputs depend only on state.
Worked example
A register has t_cq = 1.2 ns, longest combinational delay = 4.0 ns, t_setup = 0.8 ns, and clock skew = +0.3 ns (capture clock arrives later). Minimum period = 1.2 + 4.0 + 0.8 + 0.3 = 6.3 ns, so f_max = 1/6.3 ns ≈ 158.7 MHz. Reducing combinational delay to 3.0 ns would allow 5.3 ns, or 188.7 MHz, if hold remains satisfied.
Traps
- Applying the setup inequality to hold analysis.
- Treating a don’t-care as 0 and missing a simpler map grouping.
- Ignoring asynchronous reset recovery/removal timing.
- Assuming a faster clock can fix a hold violation; it cannot.