Hardware and Embedded Systems
Hardware and Embedded Systems tests microcontroller peripherals, interrupt behavior, real-time scheduling, and data conversion. Expect calculations on ADC resolution, sampling, and timing rather than block-diagram recall.
Interrupts and I/O
ISRs should be short; defer work to tasks. Shared variables between an ISR and main code must be volatile (and protected where needed). Memory-mapped I/O uses ordinary load/store instructions to device registers. DMA reduces CPU involvement in block transfers. Watchdogs recover from software lockups; debouncing removes mechanical switch bounce.
ADC and sampling
An n-bit ADC with reference Vref has LSB = Vref/2^n and quantization error up to ±0.5 LSB. Nyquist requires sampling above twice the highest signal frequency; practical designs use anti-alias filtering and often 5–10× oversampling. Sample-and-hold acquisition time depends on source impedance.
RTOS scheduling
Rate-monotonic scheduling assigns higher priority to shorter periods; earliest-deadline-first is dynamic. Priority inversion occurs when a low-priority task holds a resource needed by a high-priority task; priority inheritance or priority ceiling protocols bound the inversion. Mutexes protect shared resources; semaphores can signal events.
Worked example
A 12-bit ADC uses Vref = 3.3 V. LSB = 3.3/4096 = 0.8057 mV. Code 2048 gives 2048 × 0.8057 mV ≈ 1.650 V. Quantization uncertainty is about ±0.40 mV, and the converter cannot resolve changes smaller than one LSB.
Traps
- Forgetting the 2^n divisor and using 2^n − 1 for a full-scale ADC code.
- Sampling at exactly Nyquist with no anti-alias filter.
- Calling blocking functions inside an ISR.
- Ignoring priority inversion in a preemptive RTOS.