3.3 V FPGA driving a 5 V 74HC165 over a 45 cm ribbon at 8 MHz
A student project uses a 3.3 V Artix-7 FPGA bank (LVCMOS33) to drive a 74HC165 shift register that runs from 5 V. The boards are joined by a 45 cm unshielded ribbon cable; the serial clock is 8 MHz and the receiver samples data on the rising edge. On the bench at 1 MHz the link is perfect, but at 8 MHz about one byte in a thousand arrives shifted by one bit. A 500 MHz probe on the shift-register clock pin shows a 0–4.6 V waveform with roughly 1.8 V of overshoot and ringing near 150 MHz, consistent with a 6–7 ns round trip on the cable. The driver edge is 2 ns. The 74HC165 datasheet gives VIH(min) = 3.15 V and VIL(max) = 1.35 V at VCC = 5 V, and the FPGA output high is 3.1 V at the 8 mA the cable and input capacitance draw. Three fixes are proposed: a 1 kΩ/2 kΩ divider on each line, a 74LVC1T45 translator, or 47 Ω series resistors. Cable length and connector pinout are fixed.
1. Explain, with numbers, why the link works at 1 MHz but fails at 8 MHz. Address the DC margin and the cable behaviour separately.
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DC margin first. The driver delivers 3.1 V; the 74HC165 at VCC = 5 V needs VIH ≥ 3.15 V. The static margin is −0.05 V, i.e. already negative before any cable effect. The input stage is not guaranteed to see a high, so any perturbation decides the result. This alone means temperature or supply variations will make behaviour change.
Why 8 MHz breaks it. A 45 cm ribbon with about 7 ns/m gives ~3 ns one-way, ~6 ns round trip, so the ring sits near 1/(2 × 3 ns) ≈ 150 MHz, matching the probe. The ring decays in roughly 3–4 cycles, about 40–70 ns. At 1 MHz (1000 ns period) the line is fully settled long before the active edge, and the next edge is far from any crosstalk event. At 8 MHz the period is 125 ns; the sampling edge arrives about 60 ns after launch, still inside the decaying ring, so the receiver can cross its threshold twice and produce an extra shift - exactly the one-bit error seen. Ringing peaks at 4.6 V also exceed the 5 V rail and forward-bias the input protection structures.
Crosstalk. Ribbon conductors with a poor return path couple a fraction of the 3.3 V clock edge into the adjacent data line. Because that data line's high level is also only 3.1 V, a few hundred mV of coupled noise is enough to push it through the threshold near the sampling instant. The fault is in the interface, not in the logic design.
2. Evaluate the three proposed fixes quantitatively and recommend one, including the cheapest correct option.
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1 kΩ/2 kΩ divider. Output = 3.3 × 2/3 = 2.2 V, which is 0.95 V below VIH(min) = 3.15 V. It cannot work; it also loads the line with 667 Ω and creates a 667 Ω × 20 pF ≈ 13 ns node.
47 Ω series resistors. With a ~100 Ω ribbon and a ~20 Ω driver, 67 Ω of source impedance moves the load-end reflection coefficient from about +1 to about −0.2 and removes most of the ring; 47 Ω × 20 pF ≈ 1 ns, so edges are not slowed. But it cannot repair a −0.05 V DC margin: the link stays marginal over temperature and supply.
74LVC1T45 translator. A side at 3.3 V, B side at 5 V: output high is 5 V against a 3.15 V threshold, giving 1.85 V margin. Cost: one device per line, ~5 ns propagation, DIR/OE pins, and power sequencing so the 5 V side is not driven from the FPGA side at power-up.
Recommendation. The cheapest correct fix is to power the 74HC165 from the same 3.3 V rail: VIH becomes 0.7 × 3.3 = 2.31 V, so the 3.1 V high has 0.8 V margin and the 74HC part is fast enough at 3.3 V for 8 MHz. Add 33–47 Ω series resistors for the ringing. If the '165 must stay at 5 V, use the translator plus series damping at the source.
3. If the 74LVC1T45 translator is fitted, what else must be checked? Name the failure that would appear on the return path and one board-level check.
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The 74HC165's serial output is a 5 V CMOS driver. An LVCMOS33 input is not 5 V tolerant (absolute maximum is about 3.6 V), so the return line cannot go straight into the FPGA: it needs its own translation channel (B→A direction) or at minimum a divider that still meets the FPGA's VIH, and the same ringing analysis applies.
Checks:
- Direction and enable timing. DIR and OE must be correct before the first clock; during FPGA configuration its pins are high-Z, and the translator's behaviour with a floating A side must be defined (use a pull-down, not a floating input).
- Return path on the ribbon. A 45 cm ribbon with one ground for every 2–3 signals keeps loop inductance and crosstalk down; without adjacent returns, both directions get worse and the grounding of the second board becomes undefined.
- Propagation and skew. About 5 ns translator delay added to a 125 ns period is harmless, but the clock and data paths must be matched so the setup at the '165 input is not eaten at 8 MHz.
- Sequence. Confirm the 5 V rail rises before or with 3.3 V, and that no 5 V node feeds an unpowered 3.3 V device.