Pancyprian TS Dig. Elec. II flashcards

32 cards. Read the term and the definition here. The deck at the top of this page is optional.

Two's complement range

For n bits, signed two's complement spans from −2^(n−1) to 2^(n−1) − 1. The most significant bit carries weight −2^(n−1), so an 8-bit value ranges from −128 to +127.

Gray code property

Adjacent Gray code words differ in exactly one bit. This prevents false intermediate codes in rotary encoders and reduces errors when signals cross clock domains.

Hamming distance

The number of bit positions in which two codewords differ. A code with minimum distance d detects d−1 errors and corrects floor((d−1)/2) errors.

De Morgan's theorem

The complement of a product equals the sum of the complements, and the complement of a sum equals the product of the complements: (AB)' = A' + B' and (A+B)' = A'B'.

Canonical SOP form

A sum of minterms, one for each input combination that makes the output 1. Each minterm is a product containing every variable, complemented or not.

Universal gate

A gate type from which any Boolean function can be built. NAND and NOR are each functionally complete on their own, which is why they dominate IC libraries.

Karnaugh map grouping

Group adjacent 1-cells in rectangles of size 1, 2, 4, 8 and so on, allowing overlap and edge wrap. Each group yields one product term with variables that change eliminated.

Static-1 hazard

A brief 0 glitch on an output that should stay 1 when one input changes. Caused by unequal path delays; fixed by adding a redundant consensus term covering the transition.

Multiplexer as logic element

A 2^n-to-1 multiplexer with n select lines can implement any n-variable Boolean function by connecting each data input to the required constant 0 or 1.

Setup and hold time

Setup time is how long data must be stable before the active clock edge; hold time is how long it must remain stable after. Violations cause metastability.

JK flip-flop behaviour

When J and K are both 1, the output toggles at each clock edge. Otherwise J=1 sets and K=1 resets, removing the forbidden state of the SR latch.

Metastability

A flip-flop output hovering between logic levels after a timing violation. It resolves unpredictably after a settling time, so synchronisers are used at asynchronous inputs.

Mealy versus Moore

A Mealy machine's output depends on present state and inputs, so it reacts within the same cycle but can glitch. A Moore output depends only on state and is glitch-free.

Johnson counter states

A twisted-ring counter with n flip-flops cycles through 2n distinct states. The inverted last stage feeds the first, giving a single circulating pattern.

Universal shift register

A register that can shift left, shift right, load in parallel, and hold, selected by mode control lines. It combines SISO, SIPO, PISO and PIPO operation.

Noise margin

The voltage safety margin between a driver's output level and a receiver's required input level. High margin is V_OH − V_IH; low margin is V_IL − V_OL.

CMOS dynamic power

Power dissipated charging and discharging load capacitance: P = C·V²·f, plus short-circuit current during transitions. Static power is only leakage.

Transmission-line threshold

When a trace is longer than roughly one-sixth of the signal's wavelength (or rise time is shorter than twice the propagation delay), reflections matter and termination is required.

SRAM versus DRAM

SRAM stores each bit in a six-transistor latch and needs no refresh, but is larger and costlier. DRAM uses one transistor and capacitor per bit and must be refreshed periodically.

FPGA lookup table

A small memory that implements any Boolean function of its k inputs by storing the truth table. It is the core programmable logic element in an FPGA fabric.

Flash memory endurance

The number of erase-write cycles a cell survives before failure, typically 10^4 to 10^5 for consumer flash. Wear levelling extends effective device lifetime.

Nyquist criterion

A signal must be sampled at least twice its highest frequency component to be reconstructed without aliasing. An anti-alias filter is placed before the sampler.

ADC resolution

The smallest voltage change an ADC can distinguish: full-scale range divided by 2^n for n bits. It equals one least significant bit (LSB).

Successive-approximation ADC

A converter that binary-searches the input using a DAC and comparator, resolving one bit per step. It offers moderate speed and resolution at low power.

Quantisation error

The difference between the true analog value and its digitised representation, bounded by ±½ LSB for rounding. It sets the ideal signal-to-noise ratio of about 6.02n + 1.76 dB.

Harvard architecture

A processor with separate program and data memory buses, allowing an instruction fetch and data access in the same cycle. Common in microcontrollers and DSPs.

Memory-mapped I/O

A scheme where peripheral registers occupy addresses in the same space as memory. Ordinary load and store instructions then access peripherals without special I/O instructions.

Interrupt latency

The delay from an interrupt request to the first instruction of the service routine. It includes finishing the current instruction, context save, and vector fetch.

SPI interface

A synchronous full-duplex serial bus using separate clock, data-in, data-out and chip-select lines. It is fast and simple but needs one select line per device.

Stuck-at fault

A fault model in which a node is permanently logic 0 or 1. Test vectors must drive the node and propagate the effect to an observable output.

Boundary scan (JTAG)

IEEE 1149.1 standard using TDI, TDO, TCK and TMS to shift test data through boundary cells around device pins, testing interconnect without physical probes.

Oscilloscope bandwidth rule

Choose a scope bandwidth at least five times the highest signal frequency of interest; otherwise rise times are distorted and amplitude is under-read.