Pancyprian TS Dig. Elec. II study guide
Pancyprian TS Dig. Elec. II · Work through your exam, one topic at a time.
The Pancyprian Technical Examination – Digital Electronics II (Παγκύπρια Εξέταση Τεχνικών – Ψηφιακά Ηλεκτρονικά II) is a subject examination within Cyprus's system of technical examinations for technicians. It is intended for candidates who already have a foundation in basic electronics and now need to demonstrate competence in digital design at technician level: number systems and Boolean algebra, combinational minimisation, sequential building blocks, counters and state machines, logic families and interfacing, memory and programmable logic, data conversion, microprocessor architecture and interfacing, and test/measurement practice. The Pancyprian TS Dig. Elec. II study guide has 9 sections and about 3,328 words.
01Number systems, codes and Boolean algebra
This domain tests fluent conversion between decimal, binary, octal and hexadecimal, signed-number representations, weighted and non-weighted codes, and manipulation of Boolean expressions. Questions are usually short but unforgiving: one lost carry or a misapplied De Morgan bar changes the answer.
376 words, about 2 min02Combinational logic design and minimisation
This domain tests the path from a word specification to a minimised two-level circuit: truth tables, canonical SOP and POS, Karnaugh maps up to four variables, don't-care conditions, NAND/NOR realisation and recognition of hazards. A canonical SOP term is a product of literals for each row where the output is 1; a canonical POS term is a sum for each row where the output is 0.
397 words, about 2 min03Latches, flip-flops and sequential logic
This domain tests bistable storage elements and their timing: NOR and NAND SR latches, the transparent D latch, edge-triggered D, JK and T flip-flops, asynchronous preset and clear, setup and hold times, propagation delay and metastability. A latch is level-sensitive: while enable is active the output follows the input.
353 words, about 2 min04Counters, registers and state machines
This domain tests counting circuits, shift registers and finite-state machine design: asynchronous versus synchronous counters, modulus, ring and Johnson counters, register modes, state diagrams, state tables and Moore/Mealy output timing. An n-bit ripple counter divides by 2^n and has a ripple delay; decoding intermediate states can produce glitches.
370 words, about 2 min05Logic families, interfacing and signal integrity
This domain tests whether logic gates can drive each other reliably: voltage levels, noise margins, fan-out, open-collector and tristate outputs, level shifting, power dissipation, transmission-line effects and decoupling. DC levels: VOH is the minimum high output, VOL the maximum low output, VIH the minimum recognised high input and VIL the maximum recognised low input.
383 words, about 2 min06Memory devices and programmable logic
This domain tests memory organisation and selection, the difference between volatile and non-volatile storage, and the architecture of programmable logic from PALs and PLAs to CPLDs and FPGAs. Capacity = 2^(number of address lines) × word size.
366 words, about 2 min07Data conversion (ADC/DAC) and mixed-signal basics
This domain tests the bridge between analogue and digital: resolution and quantisation, sampling theory, ADC architectures, DAC architectures, and the specifications that determine real accuracy rather than nominal bit count. An n-bit converter has 2^n codes.
346 words, about 2 min08Microcontroller/microprocessor architecture and interfacing
This domain tests the processor core and its peripheral connections: architecture, instruction cycle, addressing modes, memory-mapped I/O, interrupts, timers, serial buses and GPIO interfacing. Von Neumann architecture shares one memory space for code and data; Harvard architecture uses separate program and data memories and can fetch instructions and data simultaneously.
349 words, about 2 min09Digital system testing, troubleshooting and measurement
This domain tests how a digital board is proved working or diagnosed when it is not: fault models, test vectors, design for testability, boundary scan, built-in self-test, and the correct use of oscilloscopes, logic analysers and multimeters. A stuck-at fault fixes a node at 0 or 1.
388 words, about 2 min