Pancyprian TS Dig. Elec. II common mistakes
Pancyprian TS Dig. Elec. II · Understand the traps and how to avoid them.
When converting a signed binary number to decimal, the candidate treats the leftmost bit as a regular place value (e.g., reads 1011 as 11 or as -3 by simple magnitude) instead of applying two's complement weight -8 to the MSB.
The candidate memorises the unsigned place-value method and applies it mechanically to all bit patterns; the special role of the sign bit in two's complement is not internalised, and the difference between sign-magnitude, one's complement and two's complement representations is blurred.
What to do instead
For every signed conversion, write the place values with a negative MSB weight (e.g., -8, +4, +2, +1 for 4 bits) and sum. Then verify by inverting all bits and adding 1 to check the magnitude. Practise mixed patterns until the negative MSB weight is automatic.
When minimising a Boolean function with a Karnaugh map, the candidate groups only adjacent 1s in pairs and misses larger groups, overlapping groups, or wraparound groups across the map edges, and fails to use don't-care cells to enlarge a group.
The candidate focuses on finding any valid group rather than the largest possible groups, and treats the map as a flat grid without recognising its toroidal adjacency. Don't-cares are often ignored because their optional status is misunderstood.
What to do instead
Before drawing groups, list the allowed group sizes (1, 2, 4, 8, 16) and always search for the largest first. Explicitly check edge wraparound and corner groups. Mark don't-care cells with X and deliberately include them when they let a group double in size. After grouping, verify by expanding each group back to its product term and confirming coverage of all 1s.
When analysing a combinational circuit with static-1 or static-0 hazards, the candidate declares the circuit hazard-free because the Boolean expression is minimised, without checking whether a single input change can momentarily produce an unwanted output pulse.
The candidate equates logical correctness with transient correctness and has not internalised that different path delays through reconvergent fan-out can create glitches even when the steady-state function is correct.
What to do instead
For each pair of adjacent 1s in the K-map that is not covered by a common group, add a consensus term (or a redundant group) to eliminate the static-1 hazard. Practise by drawing the circuit with gate delays and tracing a single-variable change through both paths. Remember that hazards are a timing phenomenon, not a logic-function error.
When deriving the next-state behaviour of a D or JK flip-flop circuit, the candidate uses the current input values to compute the next state but forgets that the flip-flop output changes only at the active clock edge, so the present-state and next-state columns are swapped or combined incorrectly.
The candidate treats the flip-flop as a combinational element and applies the excitation equations directly to the current state without separating the present-state variables from the next-state variables in the analysis table.
What to do instead
Always build an explicit state table with separate columns for present state, inputs, flip-flop inputs (D or J,K), and next state. Compute the flip-flop inputs from the present state and circuit equations, then apply the characteristic table (D: Q+=D; JK: Q+=JQ'+K'Q) to obtain the next state. Never substitute the next state back into the excitation equations within the same row.
When designing a synchronous counter with a specified modulus that is not a power of two, the candidate builds a free-running binary counter and simply ignores the unused states, without ensuring that the unused states lead back into the valid sequence on the next clock.
The candidate focuses only on the intended count sequence and does not analyse the complete state diagram, so lock-up or unintended sequences in the unused states go unnoticed.
What to do instead
Draw the full state diagram including all unused states, then add self-correcting logic (e.g., detect the unused state and force a synchronous reset or jump to state 0) so every unused state has a defined transition into the valid sequence. Verify by simulating from each unused state.
When interfacing a 3.3 V logic output to a 5 V CMOS input, the candidate connects them directly and assumes the high level will be recognised, without checking VOH versus VIH or the input clamp current.
The candidate treats logic levels as ideal 0 and 1 and does not consult the datasheet parameters VOH, VOL, VIH, VIL, or the input protection diode ratings. The difference between TTL and CMOS threshold ratios is also overlooked.
What to do instead
For every interface, compare the driver's VOH(min) with the receiver's VIH(min) and the driver's VOL(max) with the receiver's VIL(max) over the full temperature and supply range. If VOH is insufficient, use a level translator or a pull-up to the higher supply (checking that the driver is open-drain or 5 V tolerant). Also verify that the receiver's input clamp current is not exceeded during overshoot.
When sizing a memory array, the candidate calculates the number of words from the address lines but forgets to account for the data width, so a 1K x 8 memory is described as 1K bits instead of 8K bits, or the number of address lines for a given word count is off by one.
The candidate confuses word count with bit count and does not systematically apply the relationship 2^n = number of addressable words. The role of chip-select decoding in expanding word capacity is also unclear.
What to do instead
Always state capacity as (number of words) x (bits per word). For n address lines, the word count is 2^n. When expanding, use chip-select decoding for word expansion and tie data lines in parallel for bit expansion. Practise converting between kbit, kword and address-line counts until the arithmetic is automatic.
When calculating the resolution or quantisation error of an ADC, the candidate uses the number of bits as the number of levels (e.g., says an 8-bit ADC has 8 levels or a resolution of Vref/8) instead of 2^8 = 256 levels and Vref/256.
The candidate confuses the exponent with the number of levels and does not distinguish between the step size (LSB) and the maximum quantisation error, which is plus or minus half an LSB for round-to-nearest converters.
What to do instead
Memorise that an n-bit converter has 2^n levels and an LSB size of Vref/2^n (for a unipolar full-scale range). Quantisation error is at most plus or minus 0.5 LSB for an ideal mid-tread converter. Work through a numerical example for 8, 10 and 12 bits and check the result against the expected order of magnitude.
When describing memory-mapped I/O in a microcontroller, the candidate claims that an IN or OUT instruction is used to access peripherals, mixing up port-mapped I/O with memory-mapped I/O, and fails to explain how the address decoder distinguishes RAM from peripheral registers.
The candidate has learned I/O concepts from different architectures and does not connect the address map to the instruction set. The role of the chip-select and address decoding in the memory map is not visualised.
What to do instead
Draw a memory map showing the address ranges for program memory, data memory, and peripheral registers. State clearly that memory-mapped I/O uses ordinary load/store instructions and that the address decoder activates the peripheral's chip-select for its assigned range. Contrast this with port-mapped I/O, which uses separate IN/OUT instructions and a separate I/O address space.
When troubleshooting a synchronous digital board with an oscilloscope, the candidate probes a clock or high-speed data line with a long ground lead and a low-bandwidth probe, then interprets the resulting ringing and slow edges as a real circuit fault.
The candidate does not appreciate that probe loading and ground-lead inductance distort fast signals, and does not distinguish measurement artefacts from actual signal-integrity problems such as reflections, crosstalk, or insufficient setup/hold margin.
What to do instead
Use a short ground lead (or a ground spring) and a probe with adequate bandwidth (at least 3 to 5 times the highest signal frequency). Check the probe compensation before measuring. When a suspected fault appears, verify it with a second measurement method (e.g., a different probe point or a differential probe) and compare against the datasheet timing specifications before concluding that the circuit is faulty.