Pancyprian TS Dig. Elec. II key terms

A binary encoding of signed integers in which the most significant bit carries negative weight, so negation is performed by inverting every bit and adding one. It gives a single representation of zero and makes addition and subtraction share the same hardware.

A signed-number format where the leftmost bit denotes the sign and the remaining bits hold the magnitude. It has two distinct codes for zero and requires separate handling of sign and magnitude during arithmetic.

A decimal digit encoding that uses four bits per digit, with only the patterns 0000 to 1001 valid. Arithmetic on packed BCD needs correction steps because a nibble sum above nine must be adjusted by adding six.

A base-16 notation using the symbols 0 to 9 and A to F, where each digit maps exactly to four binary bits. It is widely used to write register values, memory addresses and machine code compactly.

A single extra bit appended to a data word so the total count of ones is even or odd. It detects any odd number of flipped bits but cannot locate or correct them, and it misses even-numbered errors.

A block error-correcting code that places several check bits among the data bits so each check covers a distinct combination of positions. The resulting syndrome identifies the exact bit in error, allowing single-bit correction.

An error-detection method that treats a data block as a polynomial and divides it by a fixed generator polynomial using modulo-2 arithmetic. The remainder transmitted with the data lets the receiver detect burst errors with high probability.

An ordering of binary patterns in which consecutive values differ in exactly one bit. It is used for position encoders and asynchronous interfaces because a single transition cannot produce a large erroneous reading from mixed bit delays.

The mathematical system of two-valued variables and the operations AND, OR and NOT, governed by identities such as distributivity and De Morgan's laws. It provides the formal basis for simplifying and proving logic expressions.

A rectangular arrangement of truth-table cells in Gray-code order that allows adjacent minterms to be grouped visually. Grouping the largest possible power-of-two blocks yields a minimal sum-of-products expression.

A standard expression formed by OR-ing one AND term for every row of the truth table where the output is one, with each term containing all input variables. It is unique for a given function and serves as a starting point for minimisation.

An input combination whose output value is irrelevant because that state never occurs in normal operation or its result is unused. Such cells may be grouped as either zero or one to obtain a simpler circuit.

A transient wrong output produced in combinational logic when two paths to a gate have unequal propagation delays during an input change. Static hazards can be removed by adding redundant consensus terms to the implementation.

A combinational circuit that selects one of several data inputs and routes it to a single output under the control of selection lines. It can also implement arbitrary logic functions by tying constant values to its data inputs.

A combinational block that activates exactly one of its outputs according to the binary value on its inputs. Decoders are used for address selection, chip enables and implementing logic functions as minterm generators.

A driver whose output can be logic high, logic low or a high-impedance state in which it effectively disconnects from the bus. It allows several devices to share a common wire without contention.

A transistor output stage that can only pull a line low or release it, so an external pull-up resistor produces the high level. Several such outputs may be wired together to form wired-AND buses and interrupt lines.

A fault in which two or more drivers simultaneously force a shared line to opposite levels, causing excessive current and possible device damage. It is prevented by careful enable timing and by using tri-state or open-drain outputs.

The minimum interval before the active clock edge during which data at a flip-flop input must remain stable. Violating it can cause the wrong value or metastability, and it limits the maximum clock frequency.

The minimum interval after the active clock edge during which a flip-flop input must stay unchanged. It is usually checked against the shortest data path delay in a circuit, not the longest.

An unstable condition in which a bistable element lingers between logic levels after a timing violation, resolving unpredictably after an indefinite delay. Synchronisers with two cascaded flip-flops reduce its probability of propagating.

An edge-triggered storage element that copies its data input to the output at the active clock transition and holds it until the next one. It is the basic building block of registers, counters and state machines.

A clocked flip-flop whose J and K inputs set, reset or toggle the stored bit, with both asserted producing a change of state rather than an invalid condition. It can be built from a D flip-flop plus feedback logic.

A cascade of flip-flops sharing a clock in which each stage passes its content to the next. Variants support serial-in parallel-out, parallel-in serial-out and bidirectional operation for data conversion and delay.

An asynchronous counter in which each stage clocks the following stage, so the output codes settle one after another. Its accumulated delay limits speed and can produce transient wrong codes when read.

A counter whose flip-flops are all clocked simultaneously and whose next state is computed by combinational logic. It avoids the accumulated stage delay of ripple designs and can be designed with a state-transition table.

A sequential model defined by a set of states, inputs, transitions and outputs, usually implemented as next-state and output logic around a register. Mealy outputs depend on the current input, Moore outputs only on the state.

The time between an input transition crossing a threshold and the resulting output transition reaching its threshold. It is normally specified for a given supply voltage, load capacitance and temperature range.

The voltage difference between the guaranteed output level of a driving gate and the worst-case input threshold of the receiving gate. A larger margin means the logic family tolerates more induced noise on the interconnect.

The number of logic inputs that a single output can reliably drive while keeping its levels within specification. It is limited by output current capability and by the total load capacitance that must be charged.

A momentary rise in a circuit's local ground potential caused by fast current changes flowing through package and trace inductance when many outputs switch at once. It can cause false switching and must be controlled with decoupling and ground planes.

A signal disturbance created when a travelling wave meets an impedance discontinuity and part of its energy returns toward the source. It is controlled by matching source or termination resistance to the line impedance.

A resistor network placed at a line end or driver to absorb travelling waves and suppress reflections. Series, parallel and Thevenin forms trade power consumption against signal integrity and loading.

A volatile memory cell built from a cross-coupled latch that retains data while powered, needing no refresh. Its speed and simplicity make it the usual choice for caches and small embedded data buffers.

A volatile memory storing each bit as charge on a capacitor, which must be periodically refreshed because leakage removes the charge. Its small cell size gives high density at the cost of refresh logic and slower access.

A non-volatile memory that stores charge on floating gates and is written and erased in blocks rather than single bytes. It has limited erase endurance and is used for program storage and configuration data.

A programmable logic chip containing macrocells with wide AND-OR arrays and a predictable pin-to-pin timing. It suits small glue-logic functions and fast decoding better than fine-grained field-programmable arrays.

A device containing a fabric of lookup tables, flip-flops, routing and embedded blocks that is configured after manufacture. It supports high logic density and parallel processing but needs external configuration memory.

An analogue front end that acquires an input voltage on a capacitor and freezes it during conversion. Its acquisition time and droop limit the accuracy of a successive-approximation or flash converter.

The unavoidable difference between a continuous analogue value and the nearest discrete code a converter can represent. For an ideal converter it is at most half a least significant bit, giving a signal-to-noise limit set by resolution.

A converter that tests bits from most to least significant, comparing the input against a DAC output and keeping or rejecting each trial bit. It offers good resolution at moderate speed with modest hardware.

A serial interface that frames data with start and stop bits and shifts it at an agreed baud rate without a shared clock. Both ends must match the rate closely enough to sample each bit near its centre.

An addressing scheme in which peripheral registers occupy the same address space as memory and are accessed with ordinary load and store instructions. It simplifies the instruction set but consumes part of the address map.

An asynchronous signal that suspends the current program, saves context and transfers control to a service routine. Interrupt latency and priority handling are critical in real-time embedded systems.

A controller that moves data between peripherals and memory without CPU involvement, freeing the processor for computation. It requires bus arbitration and careful buffer management to avoid data corruption.

A test structure that connects internal flip-flops into a shift register so test patterns can be loaded and results read out serially. It improves controllability and observability of sequential logic during manufacturing test.

On-chip circuitry that generates test stimuli and evaluates the responses of a block, typically producing a pass or fail signature. It enables testing at speed without external automatic test equipment.

A standardised test access architecture that places a shift-register cell at each device pin, allowing interconnect and device tests through a small serial port. It also supports in-system programming and debug access.

Adjustment of a probe's trim capacitor so its response matches the instrument input, giving a flat displayed square wave. An uncompensated probe distorts rise time and amplitude measurements.

The condition in which an arithmetic result exceeds the range representable in the available bit width. In two's complement addition it is detected when the carry into and out of the sign bit differ.