Pancyprian TS Dig. Elec. II study plan
Pancyprian TS Dig. Elec. II · Give each week a clear focus.
8 weeks · About 6 hours per week
Number systems, codes and Boolean algebra & Combinational logic design and minimisation
Convert numbers between binary, octal, decimal, and hexadecimal and perform two's-complement arithmetic without errors
Apply Boolean algebra laws and Karnaugh maps to simplify logic expressions with up to four variables
Derive canonical SOP and POS forms from truth tables and implement them with NAND/NOR gates
Identify and correct common minimisation mistakes such as static hazards and non-essential prime implicants
Your checkpoint
A handwritten or typed problem set of 15 solved conversion and minimisation exercises, with step-by-step working and a self-check against truth tables.
Combinational logic design and minimisation & Latches, flip-flops and sequential logic
Design combinational circuits for adders, comparators, multiplexers, and decoders using only basic gates
Analyse and contrast SR, D, JK, and T latches and flip-flops, including edge-triggered versus level-sensitive behaviour
Construct timing diagrams for sequential circuits given input waveforms and initial states
Explain setup and hold time violations and propose fixes such as adding buffers or adjusting clock skew
Your checkpoint
A design report containing a 4-bit ripple-carry adder schematic, a D flip-flop timing diagram, and a written explanation of one setup-time violation scenario.
Latches, flip-flops and sequential logic & Counters, registers and state machines
Design synchronous counters (up/down, modulo-N) using flip-flops and verify their state sequences
Build and analyse shift registers for serial-to-parallel and parallel-to-serial conversion
Draw state diagrams and state tables for simple Moore and Mealy machines
Convert a state diagram into a next-state logic implementation using D flip-flops and combinational logic
Your checkpoint
A complete state machine design for a traffic-light controller, including state diagram, state table, K-map minimisation, and final circuit diagram.
Counters, registers and state machines & Logic families, interfacing and signal integrity
Compare TTL, CMOS, and BiCMOS logic families on voltage levels, power dissipation, speed, and fan-out
Calculate noise margins and explain how to interface 5 V and 3.3 V logic safely
Identify signal integrity issues such as ringing, crosstalk, and ground bounce and propose mitigation techniques
Select appropriate pull-up/pull-down resistors and termination for a given bus configuration
Your checkpoint
A two-page interfacing guide that includes a level-shifter circuit, calculated noise margins for a mixed-family connection, and a checklist of signal-integrity checks.
Memory devices and programmable logic & Data conversion (ADC/DAC) and mixed-signal basics
Classify memory types (SRAM, DRAM, ROM, EPROM, EEPROM, Flash) by operation, volatility, and typical use
Explain the architecture of CPLDs and FPGAs, including logic blocks, routing, and I/O cells
Describe the ADC process (sampling, quantisation, encoding) and compare flash, SAR, and delta-sigma architectures
Calculate resolution, quantisation error, and conversion time for a given ADC/DAC specification
Your checkpoint
A comparison table of five memory technologies and three ADC architectures, plus worked calculations for an 8-bit SAR ADC with a 1 V reference.
Microcontroller/microprocessor architecture and interfacing & Digital system testing, troubleshooting and measurement
Describe the internal architecture of a typical microcontroller: CPU, memory map, GPIO, timers, interrupts, and serial interfaces
Write and explain assembly or C code for polling and interrupt-driven I/O
Design a test sequence using a logic analyser and oscilloscope to diagnose a stuck-at fault in a combinational circuit
Interpret datasheet timing diagrams to verify setup/hold compliance in a microprocessor bus cycle
Your checkpoint
A troubleshooting log for a simulated fault in a small microcontroller system, including test steps, observed waveforms (described in text), and the identified root cause.
Number systems, codes and Boolean algebra & Combinational logic design and minimisation & Latches, flip-flops and sequential logic
Re-solve mixed problems combining number systems, Boolean minimisation, and sequential logic under timed conditions
Explain the difference between combinational and sequential hazards and demonstrate one correction method
Derive the characteristic equation and excitation table for each flip-flop type from memory
Complete a full past-paper-style question set covering domains 1–3 without notes
Your checkpoint
A timed 60-minute mock test covering domains 1–3, scored and reviewed, with a list of weak areas and corrected solutions.
Counters, registers and state machines & Logic families, interfacing and signal integrity & Memory devices and programmable logic & Data conversion (ADC/DAC) and mixed-signal basics & Microcontroller/microprocessor architecture and interfacing & Digital system testing, troubleshooting and measurement
Review counter and register design pitfalls such as ripple versus synchronous behaviour and clock domain crossing
Summarise logic-family interfacing rules and signal-integrity mitigation in a one-page reference sheet
Compare memory and programmable-logic choices for a given embedded application scenario
Explain ADC/DAC selection criteria and microcontroller peripheral configuration for a mixed-signal task
Practise describing a structured troubleshooting flow for a digital system failure
Your checkpoint
A full-length mock exam (90 minutes) covering all domains, with a self-marked answer key and a final one-page formula and concept summary sheet.
Milestones
Week 4: Score at least 70% on a self-made 20-question quiz covering number systems, Boolean minimisation, and sequential logic fundamentals, and correctly draw a state diagram for a 3-state machine from memory.
Week 6: Correctly answer 8 out of 10 questions on memory types, ADC architectures, and microcontroller architecture, and produce a working level-shifter calculation for a 5 V to 3.3 V interface.
Week 8: Achieve at least 75% on the full-length mock exam and complete the one-page summary sheet without referring to notes.