Pancyprian TS Dig. Elec. II study materials
Pancyprian TS Dig. Elec. II study resources

Pancyprian TS Dig. Elec. II case studies

Pancyprian TS Dig. Elec. II · Put your knowledge to work in context.

The Pancyprian Technical Examination – Digital Electronics II (Παγκύπρια Εξέταση Τεχνικών – Ψηφιακά Ηλεκτρονικά II) is a subject examination within Cyprus's system of technical examinations for technicians. It is intended for candidates who already have a foundation in basic electronics and now need to demonstrate competence in digital design at technician level: number systems and Boolean algebra, combinational minimisation, sequential building blocks, counters and state machines, logic families and interfacing, memory and programmable logic, data conversion, microprocessor architecture and interfacing, and test/measurement practice. The Pancyprian TS Dig. Elec. II case studies are 5 cases and about 4,563 words.

1

3.3 V FPGA driving a 5 V 74HC165 over a 45 cm ribbon at 8 MHz

A student project uses a 3.3 V Artix-7 FPGA bank (LVCMOS33) to drive a 74HC165 shift register that runs from 5 V. The boards are joined by a 45 cm unshielded ribbon cable; the serial clock is 8 MHz and the receiver samples data on the rising edge.

931 words, about 5 min
2

Combinational output glitch in a six-state locker controller on a 74HC CPLD

A locker controller is a six-state Moore machine built in a 74HC-series CPLD with three state flip-flops. All outputs are decoded combinationally from the state vector; for example ALARM EN = Q2·Q1′.

924 words, about 5 min
3

SAR ADC with a high-impedance divider and a scanned multiplexer

A battery-powered pressure logger uses a bridge sensor with 0–30 mV full scale and an INA333 at G = 50, giving 0–1.500 V. A 100 kΩ/100 kΩ divider halves this to 0–0.750 V before a 4:1 analogue multiplexer (Ron = 100 Ω) and a 12-bit SAR ADC with VREF = 3.000 V and a 20 pF internal sample capacitor.

935 words, about 5 min
4

Frame buffer rows repeating: a 1 M×16 SRAM with one address line open

A display tester uses an STM32 FMC to drive a 1 M×16 asynchronous SRAM (A0–A19, 2 MB) as a 1024×768 16-bit frame buffer starting at 0x6000 0000. The image is written linearly, word address = y·1024 + x.

832 words, about 4 min
5

Spurious LCD write caused by an address-transition race on a 65C02 board

A 65C02 board runs at 1 MHz. RAM is 0x0000–0x3FFF, an HD44780 LCD occupies 0x7000–0x700F and ROM is 0xC000–0xFFFF.

941 words, about 5 min