Pancyprian TS Dig. Elec. II cheat sheet

Binary positional value: each bit i has weight 2^i; n bits represent unsigned range 0 to 2^n − 1.

Two's complement: negate by inverting all bits and adding 1; n-bit range is −2^(n−1) to 2^(n−1) − 1; the MSB is the sign bit.

Hex to binary: expand each hex digit to exactly 4 bits; binary to octal: group bits in threes from the radix point outward.

BCD encodes each decimal digit in 4 bits; invalid codes 1010–1111 must be corrected or flagged after arithmetic.

Gray code differs by one bit between adjacent values; used for encoders and asynchronous crossings; binary-to-Gray: G = B XOR (B >> 1).

Parity adds one bit so total ones are even or odd; it detects any single-bit error but cannot correct or detect even-count errors.

Hamming(7,4): 3 parity bits cover positions 1,2,4; syndrome gives the error position; single-error correction, double-error detection with an extra bit.

Signed-magnitude and one's complement both have two zeros; two's complement has a single zero, which is why ALUs use it.

Identities: A + A'B = A + B; A + AB = A; A·A' = 0; A + A' = 1; absorption A(A + B) = A.

De Morgan: (A·B)' = A' + B' and (A + B)' = A'·B'; apply by breaking the bar and swapping AND/OR.

Canonical SOP is the OR of minterms where output is 1; canonical POS is the AND of maxterms where output is 0.

Minterm m_i corresponds to the input combination equal to binary i; maxterm M_i is 0 for that same combination and M_i = m_i'.

SOP form maps directly to AND-OR or NAND-NAND two-level networks; POS maps to OR-AND or NOR-NOR.

A function is complete in NAND alone or NOR alone; AND-OR-INVERT is the native form of a NAND gate.

Consensus theorem: AB + A'C + BC = AB + A'C; the redundant term BC can be removed.

XOR identities: A XOR A = 0; A XOR 1 = A'; A XOR 0 = A; XOR is associative and used for parity and controlled inversion.

Karnaugh map: group 1s in powers-of-two rectangles (1,2,4,8), largest first, overlapping allowed, wrap edges; each group removes variables that change.

Don't-care terms may be grouped with 1s to enlarge a group but never need to be covered themselves.

Quine-McCluskey gives prime implicants systematically; a prime implicant is essential if it is the only one covering some minterm.

Hazards: a static-1 hazard appears when two adjacent 1-groups are not overlapped; add a redundant consensus term to remove it.

Multiplexer as function generator: n select lines implement any n-variable function by tying data inputs to 0 or 1.

Decoder with active-high outputs implements minterms directly; OR the required outputs to realise SOP.

Ripple-carry adder delay grows with bit width; carry-lookahead computes generate G = AB and propagate P = A XOR B in parallel.

A full adder: Sum = A XOR B XOR Cin; Cout = AB + Cin(A XOR B); a half adder lacks Cin.

Latch is level-sensitive (transparent while enable is active); flip-flop is edge-triggered and samples only at the clock edge.

SR latch with NOR gates: S = 1 sets, R = 1 resets; S = R = 1 is forbidden because it forces both outputs to 0.

D flip-flop: Q(next) = D at the active edge; it is the standard register and pipeline element.

JK flip-flop removes the forbidden state: J = K = 1 toggles; characteristic equation Q+ = JQ' + K'Q.

T flip-flop toggles when T = 1: Q+ = T XOR Q; it is a JK with J = K = T.

Setup time is the interval data must be stable before the clock edge; hold time is the interval after it; violating either causes metastability.

Propagation delay t_pd limits maximum clock: T ≥ t_pd(FF) + t_pd(logic) + t_setup.

Asynchronous preset/clear override the clock and are used for initialisation and reset; synchronous reset acts only at the edge.

An n-bit binary counter has 2^n states; a modulus-M counter needs ceil(log2 M) flip-flops and a reset or terminal-count decode at M.

Ripple (asynchronous) counters cascade Q outputs; cumulative delay limits frequency and creates decoding glitches.

Synchronous counters clock all flip-flops together; terminal count is decoded from all Q outputs to load or clear.

Johnson counter (twisted-ring) with n stages has 2n states; ring counter has n states and needs a single circulating 1.

Shift register modes: SISO, SIPO, PISO, PISO/PIPO; a universal shift register adds hold and bidirectional shift.

Mealy output depends on state and inputs (can glitch, responds in same cycle); Moore output depends on state only (registered, glitch-free).

State encoding: binary uses fewest flip-flops; one-hot uses one flip-flop per state and simplifies next-state logic in FPGAs.

FSM design flow: state diagram → state table → next-state and output equations → K-map minimisation → flip-flop implementation.

TTL logic levels: V_IH ≥ 2.0 V, V_IL ≤ 0.8 V, V_OH ≥ 2.4 V, V_OL ≤ 0.4 V; CMOS 5 V is roughly 3.5 V/1.5 V thresholds.

DC noise margin high = V_OH(driver) − V_IH(receiver); low = V_IL(receiver) − V_OL(driver); both must be positive.

Fan-out is limited by output current: I_OH ≥ N·I_IH and I_OL ≥ N·I_IL; CMOS fan-out is capacitive rather than DC-current limited.

TTL inputs left floating read as logic 1; CMOS inputs must never float or the gate draws crowbar current and oscillates.

CMOS static power is leakage only; dynamic power P = C·V²·f plus short-circuit power, so power scales with frequency.

Unused CMOS inputs tie to VDD or GND through a resistor or directly; outputs must not be wired together unless tri-state or open-drain.

Transmission-line effects appear when trace length exceeds about one-sixth of the signal wavelength; terminate series or parallel to control reflections.

Crosstalk and ground bounce are reduced by a continuous ground plane, short return paths, and decoupling capacitors near each IC.

RAM is volatile and randomly accessible; ROM is non-volatile; SRAM uses 6-transistor cells and needs no refresh, DRAM uses 1T1C and needs periodic refresh.

Memory capacity = 2^(address lines) × word width; a 2^k × n device needs k address lines and n data lines.

Address decoding: full decoding avoids aliasing; partial decoding maps the device into multiple address ranges.

Flash (EEPROM) is erased in blocks and written by page; endurance is limited to roughly 10^4–10^5 erase cycles.

PROM is one-time programmable; EPROM erased by UV; EEPROM/Flash electrically erasable.

PLD architectures: PLA has programmable AND and OR arrays; PAL has fixed OR array; GAL adds reprogrammable EEPROM cells.

FPGA uses LUTs (k-input lookup tables), configurable interconnect, and dedicated blocks (BRAM, DSP, PLL); configuration is loaded at power-up from external memory or internal flash.

CPLD is coarse-grained, non-volatile, and has predictable pin-to-pin timing; FPGA is fine-grained and volatile, needing configuration time.

Resolution = V_FS / 2^n; LSB size for an n-bit converter over full-scale range V_FS.

Quantisation error is at most ±½ LSB for rounding; SNR(dB) ≈ 6.02n + 1.76 for an ideal n-bit converter.

Sample rate must satisfy Nyquist: f_s ≥ 2·f_max; otherwise aliasing folds high frequencies into the baseband, requiring an anti-alias filter.

Successive-approximation ADC: binary search over n comparisons per sample; medium speed, medium resolution, low power.

Flash ADC uses 2^n − 1 comparators in parallel; fastest, but area and power grow exponentially.

Dual-slope (integrating) ADC averages over time, giving high resolution and noise rejection but slow conversion.

R-2R ladder DAC: binary-weighted currents summed into an op-amp; settling time and glitch energy are key specs.

Delta-sigma ADC uses oversampling and noise shaping to push quantisation noise above the band, then decimates; high resolution at low bandwidth.

Von Neumann shares one memory space for code and data; Harvard uses separate program and data buses, allowing simultaneous fetch.

CISC has variable-length instructions and microcode; RISC has fixed-length instructions, load/store architecture and pipelining.

Memory-mapped I/O places peripherals in the address space; port-mapped I/O uses separate IN/OUT instructions.

Interrupt handling: save context, vector to ISR, service, restore; latency depends on current instruction and priority masking.

Polling vs interrupts: polling wastes CPU cycles but has deterministic timing; interrupts free the CPU but add latency and re-entrancy risk.

UART is asynchronous and needs agreed baud rate; SPI is synchronous full-duplex with separate clock; I²C is two-wire with addressing and ACK.

PWM duty cycle controls average voltage; timer prescaler and period set frequency: f = f_clk / (prescaler × (period + 1)).

Watchdog timer resets the MCU if the program fails to service it within the timeout window.

Stuck-at fault model: a node is permanently 0 or 1; test vectors must propagate the fault to an observable output.

Controllability (set a node to a value) and observability (see it at an output) determine testability; scan chains improve both.

Boundary scan (JTAG, IEEE 1149.1) uses TDI, TDO, TCK, TMS to test interconnects and load configuration.

Oscilloscope: probe compensation, bandwidth ≥ 5× signal frequency, and ground lead length kept short to avoid ringing.

Logic analyser captures many channels with a clock or pattern trigger; useful for bus timing and protocol decode.

Signature analysis and BIST compare a compressed response against a known-good signature to detect faults.

Common faults: open solder joints, bridged traces, missing pull-ups, floating CMOS inputs, decoupling capacitors absent.

Divide-and-conquer troubleshooting: verify power and clock first, then reset, then bus activity, then functional blocks.

Binary positional value: each bit i has weight 2^i; n bits represent unsigned range 0 to 2^n − 1.

Two's complement: negate by inverting all bits and adding 1; n-bit range is −2^(n−1) to 2^(n−1) − 1; the MSB is the sign bit.

Hex to binary: expand each hex digit to exactly 4 bits; binary to octal: group bits in threes from the radix point outward.

BCD encodes each decimal digit in 4 bits; invalid codes 1010–1111 must be corrected or flagged after arithmetic.

Gray code differs by one bit between adjacent values; used for encoders and asynchronous crossings; binary-to-Gray: G = B XOR (B >> 1).

Parity adds one bit so total ones are even or odd; it detects any single-bit error but cannot correct or detect even-count errors.

Hamming(7,4): 3 parity bits cover positions 1,2,4; syndrome gives the error position; single-error correction, double-error detection with an extra bit.

Signed-magnitude and one's complement both have two zeros; two's complement has a single zero, which is why ALUs use it.

Identities: A + A'B = A + B; A + AB = A; A·A' = 0; A + A' = 1; absorption A(A + B) = A.

De Morgan: (A·B)' = A' + B' and (A + B)' = A'·B'; apply by breaking the bar and swapping AND/OR.

Canonical SOP is the OR of minterms where output is 1; canonical POS is the AND of maxterms where output is 0.

Minterm m_i corresponds to the input combination equal to binary i; maxterm M_i is 0 for that same combination and M_i = m_i'.

SOP form maps directly to AND-OR or NAND-NAND two-level networks; POS maps to OR-AND or NOR-NOR.

A function is complete in NAND alone or NOR alone; AND-OR-INVERT is the native form of a NAND gate.

Consensus theorem: AB + A'C + BC = AB + A'C; the redundant term BC can be removed.

XOR identities: A XOR A = 0; A XOR 1 = A'; A XOR 0 = A; XOR is associative and used for parity and controlled inversion.

Karnaugh map: group 1s in powers-of-two rectangles (1,2,4,8), largest first, overlapping allowed, wrap edges; each group removes variables that change.

Don't-care terms may be grouped with 1s to enlarge a group but never need to be covered themselves.

Quine-McCluskey gives prime implicants systematically; a prime implicant is essential if it is the only one covering some minterm.

Hazards: a static-1 hazard appears when two adjacent 1-groups are not overlapped; add a redundant consensus term to remove it.

Multiplexer as function generator: n select lines implement any n-variable function by tying data inputs to 0 or 1.

Decoder with active-high outputs implements minterms directly; OR the required outputs to realise SOP.

Ripple-carry adder delay grows with bit width; carry-lookahead computes generate G = AB and propagate P = A XOR B in parallel.

A full adder: Sum = A XOR B XOR Cin; Cout = AB + Cin(A XOR B); a half adder lacks Cin.

Latch is level-sensitive (transparent while enable is active); flip-flop is edge-triggered and samples only at the clock edge.

SR latch with NOR gates: S = 1 sets, R = 1 resets; S = R = 1 is forbidden because it forces both outputs to 0.

D flip-flop: Q(next) = D at the active edge; it is the standard register and pipeline element.

JK flip-flop removes the forbidden state: J = K = 1 toggles; characteristic equation Q+ = JQ' + K'Q.

T flip-flop toggles when T = 1: Q+ = T XOR Q; it is a JK with J = K = T.

Setup time is the interval data must be stable before the clock edge; hold time is the interval after it; violating either causes metastability.

Propagation delay t_pd limits maximum clock: T ≥ t_pd(FF) + t_pd(logic) + t_setup.

Asynchronous preset/clear override the clock and are used for initialisation and reset; synchronous reset acts only at the edge.

An n-bit binary counter has 2^n states; a modulus-M counter needs ceil(log2 M) flip-flops and a reset or terminal-count decode at M.

Ripple (asynchronous) counters cascade Q outputs; cumulative delay limits frequency and creates decoding glitches.

Synchronous counters clock all flip-flops together; terminal count is decoded from all Q outputs to load or clear.

Johnson counter (twisted-ring) with n stages has 2n states; ring counter has n states and needs a single circulating 1.

Shift register modes: SISO, SIPO, PISO, PIPO; a universal shift register adds hold and bidirectional shift.

Mealy output depends on state and inputs (can glitch, responds in same cycle); Moore output depends on state only (registered, glitch-free).

State encoding: binary uses fewest flip-flops; one-hot uses one flip-flop per state and simplifies next-state logic in FPGAs.

FSM design flow: state diagram → state table → next-state and output equations → K-map minimisation → flip-flop implementation.

TTL logic levels: V_IH ≥ 2.0 V, V_IL ≤ 0.8 V, V_OH ≥ 2.4 V, V_OL ≤ 0.4 V; CMOS 5 V is roughly 3.5 V/1.5 V thresholds.

DC noise margin high = V_OH(driver) − V_IH(receiver); low = V_IL(receiver) − V_OL(driver); both must be positive.

Fan-out is limited by output current: I_OH ≥ N·I_IH and I_OL ≥ N·I_IL; CMOS fan-out is capacitive rather than DC-current limited.

TTL inputs left floating read as logic 1; CMOS inputs must never float or the gate draws crowbar current and oscillates.

CMOS static power is leakage only; dynamic power P = C·V²·f plus short-circuit power, so power scales with frequency.

Unused CMOS inputs tie to VDD or GND through a resistor or directly; outputs must not be wired together unless tri-state or open-drain.

Transmission-line effects appear when trace length exceeds about one-sixth of the signal wavelength; terminate series or parallel to control reflections.

Crosstalk and ground bounce are reduced by a continuous ground plane, short return paths, and decoupling capacitors near each IC.

RAM is volatile and randomly accessible; ROM is non-volatile; SRAM uses 6-transistor cells and needs no refresh, DRAM uses 1T1C and needs periodic refresh.

Memory capacity = 2^(address lines) × word width; a 2^k × n device needs k address lines and n data lines.

Address decoding: full decoding avoids aliasing; partial decoding maps the device into multiple address ranges.

Flash (EEPROM) is erased in blocks and written by page; endurance is limited to roughly 10^4–10^5 erase cycles.

PROM is one-time programmable; EPROM erased by UV; EEPROM/Flash electrically erasable.

PLD architectures: PLA has programmable AND and OR arrays; PAL has fixed OR array; GAL adds reprogrammable EEPROM cells.

FPGA uses LUTs (k-input lookup tables), configurable interconnect, and dedicated blocks (BRAM, DSP, PLL); configuration is loaded at power-up from external memory or internal flash.

CPLD is coarse-grained, non-volatile, and has predictable pin-to-pin timing; FPGA is fine-grained and volatile, needing configuration time.

Resolution = V_FS / 2^n; LSB size for an n-bit converter over full-scale range V_FS.

Quantisation error is at most ±½ LSB for rounding; SNR(dB) ≈ 6.02n + 1.76 for an ideal n-bit converter.

Sample rate must satisfy Nyquist: f_s ≥ 2·f_max; otherwise aliasing folds high frequencies into the baseband, requiring an anti-alias filter.

Successive-approximation ADC: binary search over n comparisons per sample; medium speed, medium resolution, low power.

Flash ADC uses 2^n − 1 comparators in parallel; fastest, but area and power grow exponentially.

Dual-slope (integrating) ADC averages over time, giving high resolution and noise rejection but slow conversion.

R-2R ladder DAC: binary-weighted currents summed into an op-amp; settling time and glitch energy are key specs.

Delta-sigma ADC uses oversampling and noise shaping to push quantisation noise above the band, then decimates; high resolution at low bandwidth.

Von Neumann shares one memory space for code and data; Harvard uses separate program and data buses, allowing simultaneous fetch.

CISC has variable-length instructions and microcode; RISC has fixed-length instructions, load/store architecture and pipelining.

Memory-mapped I/O places peripherals in the address space; port-mapped I/O uses separate IN/OUT instructions.

Interrupt handling: save context, vector to ISR, service, restore; latency depends on current instruction and priority masking.

Polling vs interrupts: polling wastes CPU cycles but has deterministic timing; interrupts free the CPU but add latency and re-entrancy risk.

UART is asynchronous and needs agreed baud rate; SPI is synchronous full-duplex with separate clock; I²C is two-wire with addressing and ACK.

PWM duty cycle controls average voltage; timer prescaler and period set frequency: f = f_clk / (prescaler × (period + 1)).

Watchdog timer resets the MCU if the program fails to service it within the timeout window.

Stuck-at fault model: a node is permanently 0 or 1; test vectors must propagate the fault to an observable output.

Controllability (set a node to a value) and observability (see it at an output) determine testability; scan chains improve both.

Boundary scan (JTAG, IEEE 1149.1) uses TDI, TDO, TCK, TMS to test interconnects and load configuration.

Oscilloscope: probe compensation, bandwidth ≥ 5× signal frequency, and ground lead length kept short to avoid ringing.

Logic analyser captures many channels with a clock or pattern trigger; useful for bus timing and protocol decode.

Signature analysis and BIST compare a compressed response against a known-good signature to detect faults.

Common faults: open solder joints, bridged traces, missing pull-ups, floating CMOS inputs, decoupling capacitors absent.

Divide-and-conquer troubleshooting: verify power and clock first, then reset, then bus activity, then functional blocks.

Binary positional value: each bit i has weight 2^i; n bits represent unsigned range 0 to 2^n − 1.

Two's complement: negate by inverting all bits and adding 1; n-bit range is −2^(n−1) to 2^(n−1) − 1; the MSB is the sign bit.

Hex to binary: expand each hex digit to exactly 4 bits; binary to octal: group bits in threes from the radix point outward.

BCD encodes each decimal digit in 4 bits; invalid codes 1010–1111 must be corrected or flagged after arithmetic.

Gray code differs by one bit between adjacent values; used for encoders and asynchronous crossings; binary-to-Gray: G = B XOR (B >> 1).

Parity adds one bit so total ones are even or odd; it detects any single-bit error but cannot correct or detect even-count errors.

Hamming(7,4): 3 parity bits cover positions 1,2,4; syndrome gives the error position; single-error correction, double-error detection with an extra bit.

Signed-magnitude and one's complement both have two zeros; two's complement has a single zero, which is why ALUs use it.

Identities: A + A'B = A + B; A + AB = A; A·A' = 0; A + A' = 1; absorption A(A + B) = A.

De Morgan: (A·B)' = A' + B' and (A + B)' = A'·B'; apply by breaking the bar and swapping AND/OR.

Canonical SOP is the OR of minterms where output is 1; canonical POS is the AND of maxterms where output is 0.

Minterm m_i corresponds to the input combination equal to binary i; maxterm M_i is 0 for that same combination and M_i = m_i'.

SOP form maps directly to AND-OR or NAND-NAND two-level networks; POS maps to OR-AND or NOR-NOR.

A function is complete in NAND alone or NOR alone; AND-OR-INVERT is the native form of a NAND gate.

Consensus theorem: AB + A'C + BC = AB + A'C; the redundant term BC can be removed.

XOR identities: A XOR A = 0; A XOR 1 = A'; A XOR 0 = A; XOR is associative and used for parity and controlled inversion.

Karnaugh map: group 1s in powers-of-two rectangles (1,2,4,8), largest first, overlapping allowed, wrap edges; each group removes variables that change.

Don't-care terms may be grouped with 1s to enlarge a group but never need to be covered themselves.

Quine-McCluskey gives prime implicants systematically; a prime implicant is essential if it is the only one covering some minterm.

Hazards: a static-1 hazard appears when two adjacent 1-groups are not overlapped; add a redundant consensus term to remove it.

Multiplexer as function generator: n select lines implement any n-variable function by tying data inputs to 0 or 1.

Decoder with active-high outputs implements minterms directly; OR the required outputs to realise SOP.

Ripple-carry adder delay grows with bit width; carry-lookahead computes generate G = AB and propagate P = A XOR B in parallel.

A full adder: Sum = A XOR B XOR Cin; Cout = AB + Cin(A XOR B); a half adder lacks Cin.

Latch is level-sensitive (transparent while enable is active); flip-flop is edge-triggered and samples only at the clock edge.

SR latch with NOR gates: S = 1 sets, R = 1 resets; S = R = 1 is forbidden because it forces both outputs to 0.

D flip-flop: Q(next) = D at the active edge; it is the standard register and pipeline element.

JK flip-flop removes the forbidden state: J = K = 1 toggles; characteristic equation Q+ = JQ' + K'Q.

T flip-flop toggles when T = 1: Q+ = T XOR Q; it is a JK with J = K = T.

Setup time is the interval data must be stable before the clock edge; hold time is the interval after it; violating either causes metastability.

Propagation delay t_pd limits maximum clock: T ≥ t_pd(FF) + t_pd(logic) + t_setup.

Asynchronous preset/clear override the clock and are used for initialisation and reset; synchronous reset acts only at the edge.

An n-bit binary counter has 2^n states; a modulus-M counter needs ceil(log2 M) flip-flops and a reset or terminal-count decode at M.

Ripple (asynchronous) counters cascade Q outputs; cumulative delay limits frequency and creates decoding glitches.

Synchronous counters clock all flip-flops together; terminal count is decoded from all Q outputs to load or clear.

Johnson counter (twisted-ring) with n stages has 2n states; ring counter has n states and needs a single circulating 1.

Shift register modes: SISO, SIPO, PISO, PIPO; a universal shift register adds hold and bidirectional shift.

Mealy output depends on state and inputs (can glitch, responds in same cycle); Moore output depends on state only (registered, glitch-free).

State encoding: binary uses fewest flip-flops; one-hot uses one flip-flop per state and simplifies next-state logic in FPGAs.

FSM design flow: state diagram → state table → next-state and output equations → K-map minimisation → flip-flop implementation.

TTL logic levels: V_IH ≥ 2.0 V, V_IL ≤ 0.8 V, V_OH ≥ 2.4 V, V_OL ≤ 0.4 V; CMOS 5 V is roughly 3.5 V/1.5 V thresholds.

DC noise margin high = V_OH(driver) − V_IH(receiver); low = V_IL(receiver) − V_OL(driver); both must be positive.

Fan-out is limited by output current: I_OH ≥ N·I_IH and I_OL ≥ N·I_IL; CMOS fan-out is capacitive rather than DC-current limited.

TTL inputs left floating read as logic 1; CMOS inputs must never float or the gate draws crowbar current and oscillates.

CMOS static power is leakage only; dynamic power P = C·V²·f plus short-circuit power, so power scales with frequency.

Unused CMOS inputs tie to VDD or GND through a resistor or directly; outputs must not be wired together unless tri-state or open-drain.

Transmission-line effects appear when trace length exceeds about one-sixth of the signal wavelength; terminate series or parallel to control reflections.

Crosstalk and ground bounce are reduced by a continuous ground plane, short return paths, and decoupling capacitors near each IC.

RAM is volatile and randomly accessible; ROM is non-volatile; SRAM uses 6-transistor cells and needs no refresh, DRAM uses 1T1C and needs periodic refresh.

Memory capacity = 2^(address lines) × word width; a 2^k × n device needs k address lines and n data lines.

Address decoding: full decoding avoids aliasing; partial decoding maps the device into multiple address ranges.

Flash (EEPROM) is erased in blocks and written by page; endurance is limited to roughly 10^4–10^5 erase cycles.

PROM is one-time programmable; EPROM erased by UV; EEPROM/Flash electrically erasable.

PLD architectures: PLA has programmable AND and OR arrays; PAL has fixed OR array; GAL adds reprogrammable EEPROM cells.

FPGA uses LUTs (k-input lookup tables), configurable interconnect, and dedicated blocks (BRAM, DSP, PLL); configuration is loaded at power-up from external memory or internal flash.

CPLD is coarse-grained, non-volatile, and has predictable pin-to-pin timing; FPGA is fine-grained and volatile, needing configuration time.

Resolution = V_FS / 2^n; LSB size for an n-bit converter over full-scale range V_FS.

Quantisation error is at most ±½ LSB for rounding; SNR(dB) ≈ 6.02n + 1.76 for an ideal n-bit converter.

Sample rate must satisfy Nyquist: f_s ≥ 2·f_max; otherwise aliasing folds high frequencies into the baseband, requiring an anti-alias filter.

Successive-approximation ADC: binary search over n comparisons per sample; medium speed, medium resolution, low power.

Flash ADC uses 2^n − 1 comparators in parallel; fastest, but area and power grow exponentially.

Dual-slope (integrating) ADC averages over time, giving high resolution and noise rejection but slow conversion.

R-2R ladder DAC: binary-weighted currents summed into an op-amp; settling time and glitch energy are key specs.

Delta-sigma ADC uses oversampling and noise shaping to push quantisation noise above the band, then decimates; high resolution at low bandwidth.

Von Neumann shares one memory space for code and data; Harvard uses separate program and data buses, allowing simultaneous fetch.

CISC has variable-length instructions and microcode; RISC has fixed-length instructions, load/store architecture and pipelining.

Memory-mapped I/O places peripherals in the address space; port-mapped I/O uses separate IN/OUT instructions.

Interrupt handling: save context, vector to ISR, service, restore; latency depends on current instruction and priority masking.

Polling vs interrupts: polling wastes CPU cycles but has deterministic timing; interrupts free the CPU but add latency and re-entrancy risk.

UART is asynchronous and needs agreed baud rate; SPI is synchronous full-duplex with separate clock; I²C is two-wire with addressing and ACK.

PWM duty cycle controls average voltage; timer prescaler and period set frequency: f = f_clk / (prescaler × (period + 1)).

Watchdog timer resets the MCU if the program fails to service it within the timeout window.

Stuck-at fault model: a node is permanently 0 or 1; test vectors must propagate the fault to an observable output.

Controllability (set a node to a value) and observability (see it at an output) determine testability; scan chains improve both.

Boundary scan (JTAG, IEEE 1149.1) uses TDI, TDO, TCK, TMS to test interconnects and load configuration.

Oscilloscope: probe compensation, bandwidth ≥ 5× signal frequency, and ground lead length kept short to avoid ringing.

Logic analyser captures many channels with a clock or pattern trigger; useful for bus timing and protocol decode.

Signature analysis and BIST compare a compressed response against a known-good signature to detect faults.

Common faults: open solder joints, bridged traces, missing pull-ups, floating CMOS inputs, decoupling capacitors absent.

Divide-and-conquer troubleshooting: verify power and clock first, then reset, then bus activity, then functional blocks.