SAR ADC with a high-impedance divider and a scanned multiplexer
A battery-powered pressure logger uses a bridge sensor with 0–30 mV full scale and an INA333 at G = 50, giving 0–1.500 V. A 100 kΩ/100 kΩ divider halves this to 0–0.750 V before a 4:1 analogue multiplexer (Ron = 100 Ω) and a 12-bit SAR ADC with VREF = 3.000 V and a 20 pF internal sample capacitor. The ADC acquisition time is 1.2 µs and the aggregate scan rate is 40 kSPS (10 kSPS per channel). Readings of a steady pressure are stable, but whenever the scan moves from a high-pressure channel to a low-pressure channel the first sample reads about 220 mV too high and the next few samples converge. A 100 nF capacitor at the multiplexer output was removed during rework. The 3.000 V reference is derived from the 3.3 V rail through an RC filter and must be replaced by a proper reference if the budget allows. Total current must stay under 200 µA.
1. Calculate the settling error and confirm that the numbers explain the observed 220 mV.
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Source resistance. The divider's Thevenin resistance is 100 kΩ in parallel with 100 kΩ = 50 kΩ, plus the multiplexer's 100 Ω, so about 50.1 kΩ.
Time constant. With the 20 pF sample capacitor, τ = 50.1 kΩ × 20 pF ≈ 1.00 µs. The acquisition window is 1.2 µs, i.e. only 1.2 τ.
Residual. After 1.2 τ the sample capacitor has covered 1 − e^−1.2 = 1 − 0.301 = 69.9% of the step; 30% of the step from the previous channel remains. A full-scale channel change of 0.750 V therefore leaves 0.301 × 0.750 V ≈ 226 mV of error at the sampling instant, which is exactly the observed ~220 mV.
Referred to the sensor. The divider halves and the amplifier multiplies by 50, so 226 mV at the ADC corresponds to 226 mV / 25 = 9.0 mV at the bridge, i.e. 30% of the 30 mV full scale. This is a settling failure caused by the source impedance, not by ADC noise or reference drift.
In LSBs. LSB = 3.000 V / 4096 = 0.732 mV, so the error is about 309 LSB. It only appears on the first sample after a channel change, because a steady channel is already at the same voltage and needs no settling - which is why continuous readings looked stable.
2. Evaluate three fixes against the 200 µA budget: a buffer amplifier, a lower-impedance divider, and a longer acquisition time. Recommend one.
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Criterion. For less than 1 LSB of settling error, the residual must be under 1/1024, so t/τ > 6.9, i.e. τ < 1.2 µs / 6.9 = 174 ns, i.e. a source resistance below 174 ns / 20 pF ≈ 8.7 kΩ.
Lower-impedance divider. 16 kΩ/16 kΩ gives 8 kΩ Thevenin, τ = 160 ns and only 0.05% residual, but draws 3.0 V / 32 kΩ = 94 µA - nearly half the total budget, on top of the INA333 and the ADC. 22 kΩ/22 kΩ (11 kΩ, τ = 220 ns) leaves ~0.4% ≈ 3 mV ≈ 4 LSB, still visible.
Longer acquisition. The 40 kSPS aggregate is set by the control loop; halving fS doubles the acquisition only if the ADC is reconfigured, and would halve throughput. Not acceptable.
Restoring the 100 nF at the multiplexer output. With a 50 kΩ source this makes things worse: τ = 50 kΩ × 100 nF = 5 ms, so the capacitor never tracks a channel change. It only helps if placed after a buffer.
Buffer. A chopper-stabilised rail-to-rail op-amp after the divider (about 100 µA) drops the source to a few ohms and the multiplexer's 100 Ω then gives τ = 100 Ω × 20 pF = 2 ns - 600 τ in the window. Offset of a chopper part (~10 µV) referred to the bridge is negligible. It also allows a 1 MΩ divider (3 µA). Recommendation: buffer, then a small RC to the ADC.
3. Only 0.750 V of the 3.000 V reference is used. Judge whether the resolution is adequate and explain what you would change.
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What is being thrown away. 0.750 V / 0.732 mV = 1024 codes, so the converter behaves like a 10-bit ADC over the sensor range: about 2 bits are lost to range. Referred to the bridge, one LSB is 0.732 mV / (50 × 0.5) = 29 µV, which is roughly 0.1% of the 30 mV full scale. For a sensor specified at 0.1% this is borderline: quantisation alone consumes the whole error budget, before amplifier offset, reference drift and noise.
Change. Remove the divider and raise the INA333 gain to 100 so 0–30 mV maps to 0–3.000 V. That gives 4096 codes over the range and an LSB of 30 mV / 4096 = 7.3 µV, a 4× improvement. Check the headroom: the INA333 output must reach 3.000 V on a 3.3 V supply (rail-to-rail output, typically within 50 mV of the rail), and its input common-mode and reference pin must be biased mid-supply. Alternatively keep G = 50 and use a 1.024 V reference (then 0–1.500 V maps to 0–1.024 V after the divider is removed: not possible, so gain must change).
Reference quality. The rail-derived reference carries the 3.3 V rail's ripple and drift directly into the gain, which shows as a slow gain error rather than noise. A 1.024 V or 2.048 V series reference with 0.1% initial accuracy and a low tempco, plus the RC already fitted, removes that term. If the design must be ratiometric, then the bridge excitation must come from the same node as the reference.