Combinational logic design and minimisation
Scope of the domain
This domain tests the path from a word specification to a minimised two-level circuit: truth tables, canonical SOP and POS, Karnaugh maps up to four variables, don't-care conditions, NAND/NOR realisation and recognition of hazards.
Core rules
- A canonical SOP term is a product of literals for each row where the output is 1; a canonical POS term is a sum for each row where the output is 0.
- K-map groups contain 1, 2, 4, 8 or 16 cells, may wrap around edges, and should be as large as possible. Each group contributes one product term; variables that change within the group are eliminated.
- For SOP, group the 1s; for POS, group the 0s and complement each resulting sum term.
- Don't-care cells may be included only when they enlarge a group; they never need to be covered.
- A SOP expression maps directly to NAND-NAND form, and a POS expression to NOR-NOR form.
- Static-1 hazards occur when two adjacent 1s are covered by different groups; adding the consensus term removes the glitch.
Worked example
Minimise F(A,B,C)=Σm(0,1,2,5,7). Plot the 1s in an eight-cell map. Cells 0 and 2 differ only in B, so they give A'C'. Cells 1 and 5 differ only in A, so they give B'C. Cells 5 and 7 differ only in B, so they give AC. Therefore F = A'C' + B'C + AC. An equally valid minimal form is A'B' + A'C' + AC, which shows that minimal SOP is not unique. To build it with NAND gates, invert literals where needed, generate each product with a NAND, and combine the products with a final NAND.
Traps that cost marks
Circling three or six cells; missing wrap-around groups at the map edges; using every don't-care and then creating a redundant term; forgetting that POS groups produce complemented sums; and assuming a NAND gate directly replaces an OR gate without bubbles. Always check that every 1 is covered and that removing any term leaves an uncovered 1; that proves minimality for the given map.