Latches, flip-flops and sequential logic
Scope of the domain
This domain tests bistable storage elements and their timing: NOR and NAND SR latches, the transparent D latch, edge-triggered D, JK and T flip-flops, asynchronous preset and clear, setup and hold times, propagation delay and metastability.
Core rules
- A latch is level-sensitive: while enable is active the output follows the input. A flip-flop is edge-triggered: it samples the input only at the active clock edge.
- Characteristic equations: D: Q+ = D; T: Q+ = T ⊕ Q; JK: Q+ = JQ' + K'Q, giving hold, set, reset and toggle; SR: Q+ = S + R'Q with SR = 0.
- JK with J=K=1 toggles each active edge. A level-sensitive JK device can race around if the clock pulse is wider than the loop delay; master-slave or edge-triggered construction prevents this.
- Setup time is the interval before the edge during which data must be stable; hold time is the interval after the edge. Violating either can cause metastability.
- Asynchronous preset and clear override the clock and are usually active-low; they must be released synchronously when possible.
Worked example
A JK flip-flop starts at Q=0. Apply J=1, K=0 and one clock edge: set, so Q=1. Apply J=1, K=1 at the next edge: toggle, so Q=0. Apply J=0, K=1 at the next edge: reset, so Q stays 0. Apply J=0, K=0: hold, so Q remains 0. If instead the D input changes 2 ns before a rising edge while the datasheet requires 5 ns setup, the flip-flop may capture the old value or become metastable; the fix is to meet the timing window or add a synchroniser.
Traps that cost marks
Treating a latch as edge-triggered; reading active-low preset as active-high; assuming preset waits for the clock; ignoring hold time because setup was checked; and expecting Q to change immediately when D changes rather than at the next active edge.