Counters, registers and state machines
Scope of the domain
This domain tests counting circuits, shift registers and finite-state machine design: asynchronous versus synchronous counters, modulus, ring and Johnson counters, register modes, state diagrams, state tables and Moore/Mealy output timing.
Core rules
- An n-bit ripple counter divides by 2^n and has a ripple delay; decoding intermediate states can produce glitches.
- A synchronous counter clocks all flip-flops together. For a modulus N below 2^n, detect the terminal state and force the next state to zero.
- Asynchronous clear acts immediately when the decoded state appears, so the decoded state is transient; synchronous reset loads zero on the next edge.
- An n-stage ring counter has n states; an n-stage Johnson counter has 2n states and self-decodes with simple gates.
- Shift registers can be SISO, SIPO, PISO or PIPO; direction and mode are controlled by select inputs.
- Moore outputs depend only on the present state; Mealy outputs depend on state and input and can respond before the next clock edge.
Worked example
Design a mod-6 counter from a 3-bit asynchronous binary counter. The natural sequence is 000 to 111. Six states are 000,001,010,011,100,101. State 110 must not persist. Decode Q2Q1Q0 = 110 with a NAND gate: NAND(Q2,Q1) goes low at 110 and drives the active-low asynchronous clear, returning the counter to 000. State 110 exists only briefly, so it is a transient state. For a glitch-free output, use synchronous reset: decode 101 and load 000 on the next clock edge. The resulting divide-by-6 output is the MSB or a decoded terminal count, depending on the required duty cycle.
Traps that cost marks
Decoding state N instead of N-1 when using synchronous reset; ignoring the delay through the clear path in ripple counters; confusing Moore and Mealy transitions; forgetting unused states in a self-starting design; and mislabelling shift-register direction. Also check whether a counter is required to be self-starting after power-up.