Logic families, interfacing and signal integrity
Scope of the domain
This domain tests whether logic gates can drive each other reliably: voltage levels, noise margins, fan-out, open-collector and tristate outputs, level shifting, power dissipation, transmission-line effects and decoupling.
Core rules
- DC levels: VOH is the minimum high output, VOL the maximum low output, VIH the minimum recognised high input and VIL the maximum recognised low input.
- High noise margin = VOH - VIH; low noise margin = VIL - VOL. Both must be positive for a reliable interface.
- Fan-out is the smaller of IOL/IIL and IOH/IIH, not simply a count of gates.
- A floating TTL input tends high; a floating CMOS input is forbidden because it can oscillate and draw current. Unused CMOS inputs must be tied to a rail.
- Open-collector and open-drain outputs need a pull-up resistor; tristate outputs need a bus and only one active driver at a time.
- CMOS dynamic power is approximately P = C·V^2·f. Fast edges require attention to trace impedance, series termination, crosstalk and ground return.
- Decoupling capacitors close to each IC supply pin supply transient current and reduce ground bounce.
Worked example
A 5 V TTL output has VOH(min)=2.4 V and VOL(max)=0.4 V. A 5 V CMOS input has VIH(min)=3.5 V and VIL(max)=1.5 V. High margin = 2.4 - 3.5 = -1.1 V, so the high level is not guaranteed; low margin = 1.5 - 0.4 = +1.1 V, which is acceptable. The interface therefore fails only in the high state. Fixes include using a 74HCT buffer with TTL-compatible thresholds, adding a pull-up to 5 V if the driver is open-collector, or using a proper level translator. A direct connection is unreliable and temperature-dependent.
Traps that cost marks
Subtracting VIH from VOH in the wrong order; assuming any 5 V logic is compatible; ignoring input leakage and fan-out current; leaving CMOS inputs floating; and probing a fast edge with a long ground lead, which creates ringing that is not really in the circuit.