Memory devices and programmable logic
Scope of the domain
This domain tests memory organisation and selection, the difference between volatile and non-volatile storage, and the architecture of programmable logic from PALs and PLAs to CPLDs and FPGAs.
Core rules
- Capacity = 2^(number of address lines) × word size. Twelve address lines and 8-bit words give 4096 × 8 bits = 4 KB = 32 Kbit.
- SRAM stores a bit in a cross-coupled latch, typically six transistors, and needs no refresh. DRAM stores charge on a capacitor, typically one transistor and one capacitor, and must be refreshed.
- ROM, PROM, EPROM, EEPROM and flash are non-volatile; SRAM and DRAM are volatile.
- Chip select enables the device, output enable controls the data buffers and write enable controls storage. Address decoding defines the memory map.
- PAL devices have a programmable AND array and a fixed OR array; PLA devices have both arrays programmable. CPLDs use macrocells, while FPGAs use lookup tables (LUTs) and routing.
- SRAM-based FPGAs lose configuration at power-off; flash-based devices retain it.
Worked example
A 4 KB memory chip has 12 address lines, A0-A11, and eight data lines. To place it at 8000h-8FFFh, decode A15=1, A14=0, A13=0 and A12=0 while A0-A11 pass to the chip. 8000h is 1000 0000 0000 0000 and 8FFFh is 1000 1111 1111 1111, so the range is 4 KB. To build 16 KB from these chips, use four chips and a 2-to-4 decoder driven by A12 and A13, with A14 and A15 enabling the decoder. Each chip then occupies a distinct 4 KB block.
Traps that cost marks
Confusing bits with bytes; using 2^n - 1 instead of 2^n for capacity; forgetting that CS and OE are often active-low; assuming DRAM needs no refresh; and mixing PAL and PLA array programmability. Check whether an address map is stated in bytes or words, and whether chips are selected by a decoder or by individual lines.