Data conversion (ADC/DAC) and mixed-signal basics
Scope of the domain
This domain tests the bridge between analogue and digital: resolution and quantisation, sampling theory, ADC architectures, DAC architectures, and the specifications that determine real accuracy rather than nominal bit count.
Core rules
- An n-bit converter has 2^n codes. The LSB size is Vref/2^n for a unipolar ADC or DAC.
- Quantisation error is at most ±0.5 LSB for an ideal converter.
- The Nyquist criterion requires sampling at least twice the highest input frequency; otherwise aliasing folds high frequencies into the baseband. An anti-alias filter and a sample-and-hold circuit are normally required.
- Flash ADCs use 2^n - 1 comparators and are fast but large. SAR ADCs binary-search and are medium speed. Sigma-delta ADCs oversample and are high resolution. Dual-slope ADCs are accurate but slow.
- R-2R ladders produce a binary-weighted output using only two resistor values, which suits integrated DACs.
- Key specifications include INL, DNL, monotonicity, settling time, SNR and ENOB. Ideal SNR ≈ 6.02n + 1.76 dB.
Worked example
A 10-bit ADC has Vref = 5 V. LSB = 5/1024 = 4.883 mV. An input of 2.000 V corresponds to 2.000/0.004883 = 409.6, so the nearest code is 410 (or 409 if the converter truncates). A 10-bit DAC fed with code 410 outputs 410/1024 × 5 V = 2.002 V, which is within half an LSB of the input. The ideal SNR is 6.02 × 10 + 1.76 = 61.96 dB, so the effective number of bits will be lower than 10 once noise and distortion are included.
Traps that cost marks
Using 2^n - 1 in the LSB formula; ignoring aliasing because the converter is fast; omitting the sample-and-hold acquisition time; confusing DNL (step-size error) with INL (absolute deviation); and assuming a monotonic DAC from its resolution alone.