Pancyprian TS Dig. Elec. II study materials
Pancyprian TS Dig. Elec. II study resources

Pancyprian TS Dig. Elec. II: Digital system testing, troubleshooting and measurement

Pancyprian TS Dig. Elec. II · Work through your exam, one topic at a time.

All guide sections

Digital system testing, troubleshooting and measurement

Scope of the domain

This domain tests how a digital board is proved working or diagnosed when it is not: fault models, test vectors, design for testability, boundary scan, built-in self-test, and the correct use of oscilloscopes, logic analysers and multimeters.

Core rules

  • A stuck-at fault fixes a node at 0 or 1. A bridging fault shorts two nodes; an open leaves a node floating or weakly driven.
  • Test vectors apply inputs and compare outputs with the expected truth table. Good vectors detect all modelled faults and avoid redundant tests.
  • Scan design turns flip-flops into a shift chain so internal states can be loaded and observed. Boundary scan (JTAG) tests interconnects through a TAP controller and boundary-scan cells.
  • BIST generates test patterns on-chip, often with an LFSR, and compresses responses into a signature.
  • An oscilloscope measures waveform shape and timing; bandwidth should be at least about five times the highest signal frequency. A logic analyser captures many channels and decodes buses.
  • Troubleshoot in order: supply voltage, ground, clock, reset, then signal activity. Divide the circuit in half and compare expected with measured levels.

Worked example

A two-input AND gate should drive an LED high when both inputs are high, but the output stays low. A voltmeter shows 5 V on both inputs and 0 V on the output. Disconnect the gate output from the downstream load and measure again. If the output rises to about 5 V, the gate is probably good and the load or a solder bridge is pulling the node low; if it remains 0 V with both inputs high, the gate is faulty or its ground/power connection is bad. This split test distinguishes a bad driver from a bad load without unsoldering the IC.

Traps that cost marks

Using a multimeter to judge a fast clock or a brief glitch; using a scope probe with a long ground lead and misreading ringing; assuming an IC is faulty before checking power, ground, clock and reset; and ignoring loading by the probe itself.